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june 2009 doc id 7516 rev 8 1/186 1 st7263bhx st7263bdx st7263bkx st7263bex low speed usb 8-bit mcu family with up to 32 kb flash/rom, dfu capability, 8-bit adc, wdg, timer, sci and i2c features memories ? 4, 8, 16 or 32 kbytes program memory: high density flash (hdflash), or rom with readout and write protection ? in-application programming (iap) and in- circuit programming (icp) ? 384, 512 or 1024 bytes ram memory (128- byte stack) clock, reset and supply management ? run, wait, slow and halt cpu modes ? 12 or 24 mhz oscillator ? ram retention mode ? optional low voltage detector (lvd) universal serial bus (usb) interface ? dma for low speed applications compliant with usb 1.5 mbs (version 2.0) and hid specifications (version 1.0) ? integrated 3.3 v voltage regulator and transceivers ? supports usb dfu class specification ? suspend and resume operations ? 3 endpoints with programmable in/out configuration up to 27 i/o ports ? up to 8 high sink i/os (10 ma at 1.3 v) ? 2 very high sink true open drain i/os (25 ma at 1.5 v) ? up to 8 lines individually programmable as interrupt inputs 1 analog peripheral ? 8-bit a/d converter with 8 or 12 channels 2 timers ? programmable watchdog ? 16-bit timer with 2 input captures, 2 output compares, pwm output and clock input 2 communication interfaces ? asynchronous serial communications inter- face ? i2c multimaster interface up to 400 khz instruction set ? 63 basic instructions ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction ? true bit manipulation development tools ? versatile development tools (under windows) including assembler, linker, c- compiler, archiver, source level debugger, software library, hardware emulator, programming boards and gang programmers, hid and dfu software layers table 1. device summary reference part number st7263bhx st7263bh2, st7263bh6 st7263bdx st7263bd6 st7263bkx st7263bk1, st7263bk2, st7263bk4, ST7263BK6 st7263bex st7263be1, st7263be2, st7263be4, st7263be6 24 1 so34(shrink) sdip32 so24 lqfp48 (7x7) qfn40 (6x6) www.st.com
contents st7263bxx 2/186 doc id 7516 rev 8 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 reset signal (bidirectional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 oscin/oscout : input/output oscillator pin . . . . . . . . . . . . . . . . . . . . . . 13 2.3 vdd/vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 vdda / vssa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.7 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.1 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.2 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
st7263bxx contents doc id 7516 rev 8 3/186 6.2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 interrupt register (itrfre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.3 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.4 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.1 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.2 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3.3 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3.4 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.4 software watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.5 hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.1.8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.2 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
contents st7263bxx 4/186 doc id 7516 rev 8 11.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.2.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.6 summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.2.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11.3 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.3.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.3.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.3.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.4 usb interface (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.4.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.4.5 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.5 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.5.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.5.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.5.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.6 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.6.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 11.6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 11.6.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
st7263bxx contents doc id 7516 rev 8 5/186 12 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 12.1.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.1.2 immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.4 indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.1.6 indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 12.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.3.1 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . 141 13.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.6.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 13.7.1 functional ems (ele ctromagnetic susc eptibility) . . . . . . . . . . . . . . . . . 147 13.7.2 electromagnetic interference (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 13.7.3 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 148 13.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13.10 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 158 13.10.1 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 13.10.2 sci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.10.3 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
contents st7263bxx 6/186 doc id 7516 rev 8 13.11 8-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 14.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15 device configuration and ordering informati on . . . . . . . . . . . . . . . . . 172 15.1 option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.2 device ordering information and transfer of customer code . . . . . . . . . . 173 15.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.3.1 evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.3.2 development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.3.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.3.4 order codes for st7263bx development tools . . . . . . . . . . . . . . . . . . 175 15.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 16 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.1 pa2 limitation with ocmp1 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.2 unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.3 usb behavior with lvd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.4 i2c multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.5 halt mode power consumption with adc on . . . . . . . . . . . . . . . . . . . . . 182 16.6 sci wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
st7263bxx list of tables doc id 7516 rev 8 7/186 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. device pin description (qfn40, lqfp48, so34 and sdip32). . . . . . . . . . . . . . . . . . . . . . 17 table 4. device pin description (so24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. interrupt vector map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. hardware register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 7. sectors available in flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. recommended values for 24 mhz crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 10. i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. port a0, a3, a4, a5, a6, a7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 table 12. pa1, pa2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13. port b description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 14. port c description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 15. port d description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 16. i/o ports register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 17. watchdog timing (fcpu = 8 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 18. watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 19. ic/r register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 20. oc/r register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 21. low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 22. interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 23. summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 24. clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 25. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 26. frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 27. low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 28. interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 29. prescaling factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 30. tr dividing factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 31. rr dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 32. sci register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 33. tp bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 34. stat_tx bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 35. stat_rx bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 36. usb register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 table 37. slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 38. slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 39. master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 40. master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 41. low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 42. interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 43. i2c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 44. low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 45. channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 46. adc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 47. addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 48. st7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 0
list of tables st7263bxx 8/186 doc id 7516 rev 8 table 49. inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 50. immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 51. instructions supporting direct, indexed, in direct and indirect indexed addressing modes133 table 52. instructions supporting relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 53. instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 54. instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 55. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 57. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 56. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 table 58. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 59. operating conditions with lvd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 60. supply current characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 61. general timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 62. control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 63. external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 64. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 65. dual voltage flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 66. emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 67. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 68. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 69. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 70. general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 71. output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 72. asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 73. usb dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 74. usb low-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 75. sci characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 76. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 77. scl frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 78. 8-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 79. adc accuracy with vdd=5 v, fcpu= 8 mhz, fadc=4 mhz, rain< 10 ?. . . . . . . . . . . . .163 table 80. 32-pin plastic dual in-line package, shrink 400-mil width, package mechanical data . . . . 166 table 81. 34-pin plastic small outline package, 300-mil width, package mechanical data . . . . . . . . 167 table 82. 24-pin plastic small outline package, 300-mil width package mechanical data . . . . . . . . 168 table 83. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 84. 40-lead very thin fine pitch quad flat no-l ead package mechanical data . . . . . . . . . . . . . 170 table 85. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 86. supported order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 87. development tool order codes for the st7263bx family . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 88. st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 89. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
st7263bxx list of figures doc id 7516 rev 8 9/186 list of figures figure 1. general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. 48-pin lqfp pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. 40-lead qfn package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. 34-pin so package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. 32-pin sdip package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. 24-pin so package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 9. typical icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11. cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 12. low voltage detector functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 13. low voltage reset signal output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 14. temporization timing diagram after an internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15. reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. external clock source connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 17. crystal/ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18. clock block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19. interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 20. halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21. wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 22. pa0, pa3, pa4, pa5, pa6, pa7 and pd[7:4] configuration . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 23. pa1, pa2 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 24. port b and d[3:0] configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 25. port c configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 26. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 27. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 28. 16-bit read sequence (from either the counter register or the alternate counter register) 61 figure 29. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 30. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 31. counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 32. input capture block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 33. input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 34. output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 35. output compare timing diagram, ftimer = fcpu/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 36. output compare timing diagram, ftimer = fcpu/4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 37. one pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 38. one pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 39. pulse width modulation mode timing with 2 output compare functions . . . . . . . . . . . . . . . 70 figure 40. pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 41. sci block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 42. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 43. bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 44. usb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 45. dma buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 46. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 47. i2c interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 48. transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
list of figures st7263bxx 10/186 doc id 7516 rev 8 figure 49. event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 50. adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 51. adc conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 52. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 53. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 54. fcpu maximum operating frequency versus v dd supply voltage . . . . . . . . . . . . . . . . . . . 141 figure 55. typ. idd in run at fcpu = 4 and 8 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 56. typ. idd in wait at fcpu= 4 and 8 mhz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 57. typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 58. typical application with a crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 figure 59. two typical applicat ions with vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 46 figure 60. two typical applications with unused i/o pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 61. typ. ipu vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 62. typ. rpu vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 63. vol standard vdd=5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 64. vol high sink vdd=5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 65. vol very high sink vdd=5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 66. vol standard vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 67. vol high sink vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 68. vol very high sink vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 69. |vdd-voh| @ vdd=5 v (low current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 70. |vdd-voh| @ vdd=5 v (high current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 71. |vdd-voh| @ iio=2 ma (low current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 72. |vdd-voh| @ iio=10 ma (high current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 73. reset pin protection when lvd is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 74. reset pin protection when lvd is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 75. usb data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 76. typical application with i2c bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 77. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 78. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 79. 32-pin plastic dual in-line package, shrink 400-mil width, package outline. . . . . . . . . . . . 166 figure 80. 34-pin plastic small outline package, 300-mil width, package outline. . . . . . . . . . . . . . . . 167 figure 81. 24-pin plastic small outline package, 300-mil width package outline . . . . . . . . . . . . . . . . 168 figure 82. 48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 figure 83. 40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 170 figure 84. option list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 figure 85. identifying silicon revision from device marking and box label . . . . . . . . . . . . . . . . . . . . . 183
st7263bxx introduction doc id 7516 rev 8 11/186 1 introduction the st7263b microcontrollers form a sub-fa mily of the st7 mcus dedicated to usb applications. the devices are based on an industry-standard 8-bit core and feature an enhanced instruction set. they operate at a 24 mhz or 12 mh z oscillator frequency. under software control, the st7263b mcus may be placed in either wait or halt modes, thus reducing power consumption. the enhanced instruction set and addressing modes afford real programming potential. in addition to standard 8-bit data management, the st7263b mcus feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. the devices include an st7 core, up to 32 kbytes of program memory, up to 1024 bytes of ram, 27 i/o lines and the following on-chip peripherals: usb low speed interface with 3 endpoints with programmable in/out configuration using the dma architecture with embedded 3.3 v voltage regulator and transceivers (no external components are needed). 8-bit analog-to-digital converter (adc) with 12 multiplexed analog inputs industry standard asynchronous sci serial interface watchdog 16-bit timer featuring an external clock input, 2 input captures, 2 output compares with pulse generator capabilities fast i2c multimaster interface low voltage reset (lvd) ensuring proper power-on or power-off of the device the st72f63b devices are flash versions. they support programming in iap mode (in- application programming) via the on-chip usb interface. table 2. device overview features st7263bhx st7263bdx st7263bkx st7263bex program memory - kbytes (flash / rom) 32 16 8 32 32 16 8 4 32 16 8 4 ram (stack) - bytes 1024 (128) 512 (128) 384 (128) 1024 (128) 1024 (128 512 (128) 384 (128) 384 (128 1024 (128) 512 (128) 384 (128) 384 (128) standard peripherals watchdog timer, 16-bit timer, usb other peripherals sci, i2c, adc sci, ad adc sci, i2c i/os (high current) 27 (10) 19 (10) 14 (6) operating supply 4.0 v to 5.5 v cpu frequency 8 mhz (with 24 mhz oscillator) or 4 mhz (with 12 mhz oscillator) operating temp. 0c to +70c packages lqfp48 (7x7) qfn40 (6x6) sdip32/ so34 qfn40 (6x6) sdip32/ so34 so24
introduction st7263bxx 12/186 doc id 7516 rev 8 figure 1. general block diagram 1. adc channels: 12 on 48-pin devices (port b and port d[3:0]) 8 on 34 and 32-pin devices (port b) none on 24-pin devices 2. 12 or 24 mhz oscin frequency required to generate 6 mhz usb clock. 3. the drive from usbvcc is sufficient to only drive an external pull-up in addition to t he internal transceiver. 8-bit core alu address and data bus oscin oscout reset port b 16-bit timer port a port c pb[7:0] (8 bits) pc[2:0] (3 bits) oscillator internal clock control ram (1024 bytes) pa[7:0] (8 bits) v ss v dd power supply sci program (32k bytes) i2c memory adc (1) (uart) usb sie osc/3 lvd watchdog v ssa v dda v pp/test usb dma usbdp usbdm usbvcc osc/4 or osc/2 for usb 2) port d pd[7:0] (8 bits)
st7263bxx pin description doc id 7516 rev 8 13/186 2 pin description 2.1 reset signal (bidirectional) it is active low and forces the initialization of the mcu. this event is the top priority non maskable interrupt. this pin is switched lo w when the watchdog is triggered or the v dd is low. it can be used to reset external peripherals. note: adding two 100 nf decoupling capacitors on the reset pin (respectively connected to v dd and v ss ) will significantly improve product elec tromagnetic susceptibility performance. 2.2 oscin/oscout: input/output oscillator pin these pins connect a parallel-resonant crystal, or an external source, to the on-chip oscillator. 2.3 v dd /v ss main power supply and ground voltages note: to enhance the reliab ility of operation, it is recommended that v dda and v dd be connected together on the application board. this also applies to v ssa and v ss . 2.4 v dda /v ssa power supply and ground voltages for analog peripherals. note: to enhance the reliab ility of operation, it is recommended that v dda and v dd be connected together on the application board. this also applies to v ssa and v ss . 2.5 alternate functions several pins of the i/o ports assume software programmable alternate functions as shown in the pin description. note: 1 the usboe alternate function is mapped on port c2 in 32/34/48 pin devices. in so24 devices it is mapped on port b1. 2 the timer ocmp1 alternate function is mapped on port a6 in 32/34/48 pin devices. in so24 devices it is not available.
pin description st7263bxx 14/186 doc id 7516 rev 8 figure 2. 48-pin lqfp pinout nc nc nc nc nc nc ain7/it8/pb7 (10ma) ain6/it7/pb6 (10ma) tdo/pc1 rdi/pc0 reset nc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 v dda v dd oscout oscin vss usboe/pc2 nc nc v ssa usbdp usbdm usbv cc pa7/ocmp2/it4 pb0 (10ma) /ain0 pb1 (10ma) /ain1 pb2 (10ma) /ain2 pb3 (10ma) /ain3 pb4 (10ma) /ain4/it5 pb5 (10ma) /ain5/it6 v pp /test pa3/extclk pa4/icap1/it1 pa5/icap2/it2 pa6/ocmp1/it3 pd5 pd4 pd3/ain11 pd2/ain10 pd1/ain9 pd0/ain8 pa 2 (25ma) /scl/iccc nc pa 0 / m c o pa 1 (25ma) /sda/iccd pd7 pd6 24
st7263bxx pin description doc id 7516 rev 8 15/186 figure 3. 40-lead qfn package pinout 1. port d functions are not available on the 8 kbyte version of the qfn40 package (st7263bk2) and should not be connected. 4 3 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 2 1 35 36 13 14 v dda v dd oscout oscin vss usboe/pc2 v ssa usbdp usbdm usbv cc nc it8/ain7/pb7 (10ma) it7/ain6/pb6 (10ma) tdo/pc1 rdi/pc0 reset nc it6/ain5/pb5 (10ma) v pp /test pa7/ocmp2/it4 pb0 (10ma) /ain0 pb1 (10ma) /ain1 pb2 (10ma) /ain2 pb3 (10ma) /ain3 pb4 (10ma) /ain4/it5 pa3/extclk pa4/icap1/it1 pa5/icap2/it2 pa6/ocmp1/it3 pd5 1) pd4 1) pd3 1) /ain11 pd2 1) /ain10 pd1 1) /ain9 pd0 1) /ain8 pa 2 (25ma) /scl/iccc pa 1 (25ma) /sda/iccd pd7 1) pd6 1) pa 0 / m c o
pin description st7263bxx 16/186 doc id 7516 rev 8 figure 4. 34-pin so package pinout figure 5. 32-pin sdip package pinout figure 6. 24-pin so package pinout 18 19 20 21 22 23 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v dd oscout ain4/it5/pb4 (10ma) ain5/it6/pb5 (10ma) v pp /test ain6/pb6/it7 (10ma) ain7/it8/pb7 (10ma) nc reset pc0/rdi pc1/tdo pc2/usboe v ss oscin usbdp v ssa pb0 (10ma) /ain0 pa7/ocmp2/it4 pa6/ocmp1/it3 pa5/icap2/it2 pa4/icap1/it1 pa3/extclk pa 2 (25ma) /scl/iccclk nc nc nc pa 1 (25ma) /sda/iccdata pa 0 / m c o 15 16 17 ain1/pb1 (10ma) ain2/pb2 (10ma) ain3/pb3 (10ma) 34 33 32 v dda usbvcc usbdm 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 29 30 31 32 v dd oscout ain1/pb1/ (10ma) ain2/pb2 (10ma) ain3/pb3 (10ma) ain4/it5/pb4 (10ma) ain5/it6/pb5 (10ma) v pp /test ain6/it7/pb6 (10ma) pc0/rdi pc1/tdo pc2/usboe v ss oscin ain7/it8/pb7 (10ma) reset v dda usbvcc pb0 (10ma) /ain0 pa7/ocmp2/it4 pa6/ocmp1/it3 pa5/icap2/it2 pa4/icap1/it1 pa3/extclk pa 2 (25ma) /scl/iccclk pa 1 (25ma) /sda/iccdata pa 0 / m c o v ssa usbdp usbdm nc nc 14 13 11 12 15 16 17 18 pa 2 (25ma) /scl/iccclk pa 1 (25ma) /sda/iccdata pa 0 / m c o v ssa pa7/ocmp2/it4 pa5/icap2/it2 pa4/icap1/it1 1 2 3 4 5 6 7 8 9 10 v dd rdi/pc0 tdo/pc1 v ss pa3/extclk it7/pb6 (10ma) 19 20 v pp /test pb3 (10ma) pb2 (10ma) usbdp reset / oscout usboe/pb1 (10ma) pb0 (10ma) oscin 21 22 23 24 usbdm usbvcc
st7263bxx pin description doc id 7516 rev 8 17/186 legend / abbreviations for table 3 and table 4 : type: i = input, o = output, s = supply in/output level:c t = cmos 0.3v dd /0.7v dd with input trigger output level: 10 ma = 10ma high sink (fn n-buffer only) 25 ma = 25 ma very high sink (on n-buffer only) port and control configuration: input:float = floating, wpu = weak pull-up, int = interrupt, ana = analog output: od = open drain, pp = push-pull, t = true open drain the reset configuration of each pin is shown in bold. this configuration is ke pt as long as the device is under reset state. table 3. device pin description (qfn40, lqfp48, so34 and sdip32) pin n pin name type level port /control main function (after reset) alternate function sdip32 so34 qfn40 lqfp48 input output input output float wpu int ana od pp 1176v dd s power supply voltage (4- 5.5 v) 2287oscout o oscillator output 3398oscin i oscillator input 44109v ss s digital ground 5 5 11 10 pc2/usboe i/o ct x x port c2 usb output enable 6 6 12 13 pc1/tdo i/o ct x x port c1 sci transmit data output 7 7 13 14 pc0/rdi i/o ct x x port c0 sci receive data input 8 8 14 15 reset i/o x x reset - 9 15 16 nc -- not connected - - 16 17 nc -- not connected - - - 18 nc -- not connected - - - 19 nc -- not connected - - - 20 nc -- not connected - - - 21 nc -- not connected - - - 22 nc -- not connected 9 10 17 23 pb7/ain7/it8 i/o ct 10ma x x x x port b7 adc analog input 7 10 11 18 24 pb6/ain6/it7 i/o ct 10ma x x x x port b6 adc analog input 6 11 12 19 25 v pp /test s programming supply 12 13 20 26 pb5/ain5/it6 i/o ct 10ma x x x x port b5 adc analog input 5 13 14 21 27 pb4/ain4/it5 i/o ct 10ma x x x x port b4 adc analog input 4 14 15 22 28 pb3/ain3 i/o ct 10ma x x x port b3 adc analog input 3
pin description st7263bxx 18/186 doc id 7516 rev 8 15 16 23 29 pb2/ain2 i/o ct 10ma x x x port b2 adc analog input 2 16 17 24 30 pb1/ain1 i/o ct 10ma x x x port b1 adc analog input 1 17 18 25 31 pb0/ain0 i/o ct 10ma x x x port b0 adc analog input 0 18 19 26 32 pa7/ocmp2/it4 i/o ct x x x port a7 timer output compare 2 19 20 27 33 pa6/ocmp1/it3 i/o ct x x x port a6 timer output compare 1 20 21 28 34 pa5/icap2/it2 i/o ct x x x port a5 timer input capture 2 21 22 29 35 pa4/icap1/it1 i/o ct x x x port a4 timer input capture 1 22 23 30 36 pa3/extclk i/o ct x x port a3 timer external clock 23 24 31 38 pa2/scl/iccclk i/o c t 25ma x t port a2 i2c serial clock, icc clock - - 32 39 pd0 (1) /ain8 i/o c t x x x port d0 adc analog input 8 - - 33 40 pd1 (1) /ain9 i/o c t x x x port d1 adc analog input 9 - - 34 41 pd2 (1) /ain10 i/o c t xxxport d2 adc analog input 10 - - 35 42 pd3 (1) /ain11 i/o c t xxxport d3 adc analog input 11 - - 36 43 pd4 (1) i/o c t xxport d4 - - 37 44 pd5 (1) i/o c t xxport d5 - - 38 45 pd6 (1) i/o c t xxport d6 - - 39 46 pd7 (1) i/o c t xxport d7 - 25 - - nc -- not connected 24 26 - - nc -- not connected 25 27 - - nc -- not connected 26 28 40 47 pa1/sda/iccdata i/o ct 25ma x t port a1 i2c serial data, icc data 27 29 1 48 pa0/mco i/o ct x x port a0 main clock output 28 30 2 1 v ssa s analog ground 29 31 3 2 usbdp i/o usb bidirectional data (data +) 30 32 4 3 usbdm i/o usb bidirectional data (data -) table 3. device pin description (qfn40, lqfp48, so34 and sdip32) (continued) pin n pin name type level port /control main function (after reset) alternate function sdip32 so34 qfn40 lqfp48 input output input output float wpu int ana od pp
st7263bxx pin description doc id 7516 rev 8 19/186 31 33 5 4 usbvcc (2) o usb power supply 2) 32 34 6 5 v dda s analog supply voltage 1. port d functions are not availabl e on the 8 kbyte version of the qfn40 package (st7263bk2) and should not be connected. 2. the drive from usbvcc is sufficient to only drive an ex ternal pull-up in addition to the internal transceiver. table 3. device pin description (qfn40, lqfp48, so34 and sdip32) (continued) pin n pin name type level port /control main function (after reset) alternate function sdip32 so34 qfn40 lqfp48 input output input output float wpu int ana od pp table 4. device pin description (so24) pin n pin name type level port /control main function (after reset) alternate function so24 input output input output float wpu int ana od pp 1v dd s power supply voltage (4- 5.5 v) 2 oscout o oscillator output 3 oscin i oscillator input 4v ss s digital ground 5 pc1/tdo i/o ct x x port c1 sci transmit data output 6 pc0/rdi i/o ct x x port c0 sci receive data input 7 reset i/o x x reset 8 pb6/it7 i/o ct 10ma x x x x port b6 9v pp /test s programming supply 10 pb3 i/o ct 10ma x x x port b3 11 pb2 i/o ct 10ma x x x port b2 12 pb1/usboe i/o ct 10ma x x x port b1 usb output enable 13 pb0 i/o ct 10ma x x x port b0 14 pa7/ocmp2/it4 i/o ct x x x port a7 timer output compare 2 15 pa5/icap2/it2 i/o ct x x x port a5 timer input capture 2 16 pa4/icap1/it1 i/o ct x x x port a4 timer input capture 1 17 pa3/extclk i/o ct x x port a3 timer external clock 18 pa2/scl/ iccclk i/o c t 25ma x t port a2 i2c serial clock, icc clock 19 pa1/sda/iccdata i/o ct 25ma x t port a1 i2c serial data, icc data
pin description st7263bxx 20/186 doc id 7516 rev 8 20 pa0/mco i/o ct x x port a0 main clock output 21 v ssa s analog ground 22 usbdp i/o usb bidirectional data (data +) 23 usbdm i/o usb bidirectional data (data -) 24 usbvcc o usb power supply table 4. device pin description (so24) (continued) pin n pin name type level port /control main function (after reset) alternate function so24 input output input output float wpu int ana od pp
st7263bxx register and memory map doc id 7516 rev 8 21/186 3 register and memory map as shown in figure 7 , the mcu is capable of addressing 32 kbytes of memories and i/o registers. the available memory locations consist of up to 1024 bytes of ram including 64 bytes of register locations, and up to 32k bytes of user program memory in which the upper 32 bytes are reserved for interrupt vectors. the ram space includes up to 128 bytes for the stack from 0100h to 017fh. the highest address bytes contain the user reset and interrupt vectors. caution: memory locations noted ?reserved? must never be accessed. accessing a reserved area can have unpredictable effects on the device. figure 7. memory map 0000h ram program memory (4 / 8 / 16 / 32 kbytes) interrupt & reset vectors hw registers 0040h 003fh ffdfh ffe0h ffffh reserved stack (128 bytes) 0100h 017fh 01c0 / 0240 / 0440h 00ffh 0040h 0180h 01bf / 023f / 043fh short addressing ram (192 bytes) 16-bit addressing ram 8000h 7fffh (see table 5) (see table 4) (384 / 512 / 1024 bytes) 8000h ffdfh f000h e000h c000h 32 kbytes 16 kbytes 8 kbytes 4 kbytes 01bf / 023f / 043fh table 5. interrupt vector map vector address description masked remarks exit from halt ffe0h-ffedh ffeeh-ffefh fff0h-fff1h fff2h-fff3h fff4h-fff5h fff6h-fff7h fff8h-fff9h fffah-fffbh fffch-fffdh fffeh-ffffh reserved area usb interrupt vector sci interrupt vector i2c interrupt vector timer interrupt vector it1 to it8 interrupt vector usb end suspend mode interrupt vector flash start programming interrupt vector trap (software) interrupt vector reset vector i- bit i- bit i- bit i- bit i- bit i- bit i- bit none none internal interrupt internal interrupt internal interrupt internal interrupt external interrupt external interrupts internal interrupt cpu interrupt no no no no ye s ye s ye s no ye s
register and memory map st7263bxx 22/186 doc id 7516 rev 8 table 6. hardware register memory map address block register label register name reset status remarks 0000h 0001h port a pa d r paddr port a data register port a data direction register 00h 00h r/w r/w 0002h 0003h port b pbdr pbddr port b data register port b data direction register 00h 00h r/w r/w 0004h 0005h port c pcdr pcddr port c data register port c data direction register 1111 x000b 1111 x000b r/w r/w 0006h 0007h port d pddr pdddr port d data register port d data direction register 00h 00h r/w r/w 0008h itc itifre interrupt register 00h r/w 0009h misc miscr miscellaneous register 00h r/w 000ah 000bh adc adcdr adccsr adc data register adc control status register 00h 00h read only r/w 000ch wdg wdgcr watchdog control register 7fh r/w 000dh to 0010h reserved (4 bytes) 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh tim tcr2 tcr1 tcsr tic1hr tic1lr toc1hr toc1lr tchr tclr tachr tac l r tic2hr tic2lr toc2hr toc2lr timer control register 2 timer control register 1 timer control/status register timer input capture high register 1 timer input capture low register 1 timer output compare high register 1 timer output compare low register 1 timer counter high register timer counter low register timer alternate counter high register timer alternate counter low register timer input capture high register 2 timer input capture low register 2 timer output compare high register 2 timer output compare low register 2 00h 00h 00h xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w r/w read only read only r/w r/w read only r/w read only r/w read only read only r/w r/w 0020h 0021h 0022h 0023h 0024h sci scisr scidr scibrr scicr1 scicr2 sci status register sci data register sci baud rate register sci control register 1 sci control register 2 c0h xxh 00h x000 0000b 00h read only r/w r/w r/w r/w
st7263bxx register and memory map doc id 7516 rev 8 23/186 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h usb usbpidr usbdmar usbidr usbistr usbimr usbctlr usbdaddr usbep0ra usbep0rb usbep1ra usbep1rb usbep2ra usbep2rb usb pid register usb dma address register usb interrupt/dma register usb interrupt status register usb interrupt mask register usb control register usb device address register usb endpoint 0 register a usb endpoint 0 register b usb endpoint 1 register a usb endpoint 1 register b usb endpoint 2 register a usb endpoint 2 register b x0h xxh x0h 00h 00h 06h 00h 0000 xxxxb 80h 0000 xxxxb 0000 xxxxb 0000 xxxxb 0000 xxxxb read only r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0032h to 0036h reserved (5 bytes) 0032h 0036h reserved (5 bytes) 0037h flash fcsr flash control /status register 00h r/w 0038h reserved (1 byte) 0039h 003ah 003bh 003ch 003dh 003eh 003fh i2c i2cdr i2coar i2cccr i2csr2 i2csr1 i2ccr i2c data register reserved i2c (7 bits) slave address register i2c clock control register i2c 2nd status register i2c 1st status register i2c control register 00h - 00h 00h 00h 00h 00h r/w r/w r/w read only read only r/w table 6. hardware register memory map (continued) address block register label register name reset status remarks
flash program memory st7263bxx 24/186 doc id 7516 rev 8 4 flash program memory 4.1 introduction the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using an external v pp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) or iap (in-application programming). the array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features 3 flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be programmed or erased. ? icp (in-circuit programming). in this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. ? iap (in-application programming). in this mode, all sectors except sector 0, can be programmed or erased without removing the device from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram readout protection register access security sy stem (rass) to prevent accid ental programmin g or erasing 4.3 structure the flash memory is organized in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, there are up to three user sectors (see ta b l e 7 ). each of these sectors can be erased independently to avoid unnecessary erasing of the whole flas h memory when only a partial erasing is required. the first two sectors have a fixed size of 4 kbytes (see figure 8 ). they are mapped in the upper part of the st7 addressing space so the reset and interrupt vectors are located in sector 0 (f000h-ffffh). table 7. sectors available in flash devices flash size (kbytes) available sectors 4sector 0 8 sectors 0,1 > 8 sectors 0,1, 2
st7263bxx flash program memory doc id 7516 rev 8 25/186 4.3.1 readout protection readout protection, when selected, provides a protection against program memory content extraction and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. in flash devices, this protection is removed by reprogramming the option. in this case, the entire program memory is first automatically erased and the device can be reprogrammed. readout protection selection depends on the device type: in flash devices it is enabled and removed through the fmp_r bit in the option byte. in rom devices it is enabled by mask option specified in the option list. figure 8. memory map and sector address 4.4 icc interface icc (in-circuit communication) needs a minimum of four and up to six pins to be connected to the programming tool (see figure 9 ). these pins are: reset : device reset v ss : device power supply ground iccclk: icc output serial clock pin iccdata: icc input/output serial data pin iccsel/v pp : programming voltage osc1(or oscin): main clock input for external source (optional) v dd : application board power supply (see figure 9 , note 3) 4 kbytes 4 kbytes 2kbytes sector 1 sector 0 16 kbytes sector 2 8k 16k 32k 60k flash ffffh efffh dfffh 3fffh 7fffh 1000h 24 kbytes memory size 8kbytes 40 kbytes 52 kbytes 9fffh bfffh d7ffh 4k 10k 24k 48k
flash program memory st7263bxx 26/186 doc id 7516 rev 8 figure 9. typical icc interface 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmi ng tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not availabl e for the application. if they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. refer to the programming tool docum entation for recommended resistor values. 2. during the icc session, the programming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset ci rcuit if it driv es more than 5ma at high level (push pull output or pull-up resist or<1k). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc netwo rk with r > 1k or a reset management ic with open drain output and pull-up resistor > 1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application dur ing the icc session. 3. the use of pin 7 of the icc connector depends on t he programming tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the osc1 or oscin pin of the st7 when the clock is not available in the application or if the select ed clock option is not programmed in t he option byte. st7 devices with multi- oscillator capability need to have osc2 grounded in this case. 4.5 icp (in-circuit programming) to perform icp the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). when using an stmicroelectronics or third-party programming tool that supports icp and the specific microcontroller device, the user needs only to implement the icp hardware interface on the application board (see figure 9 ). for more details on the pin locations, refer to the device pinout description. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) 10k v ss iccsel/vpp st7 c l2 c l1 osc1 osc2 optional see note 1 see note 2 application reset source application i/o (see note 4)
st7263bxx flash program memory doc id 7516 rev 8 27/186 4.6 iap (in-application programming) this mode uses a bootloader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the sci or other type of serial interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. 4.7 related documentation for details on flash programming and icc protocol, refer to the st7 flash programming reference manual and to the st7 icc protocol reference manual . 4.8 register description flash control/status register (fcsr) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. reset value: 0000 0000 (00h) 76543210 00000000 read/write
central processing unit st7263bxx 28/186 doc id 7516 rev 8 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 5.3 cpu registers the six cpu registers shown in figure are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the following instruction refers to the y register.) the y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb).
st7263bxx central processing unit doc id 7516 rev 8 29/186 condition code register (cc) reset value: 111x1xxx the 8-bit condition code register contains the interrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. 76543210 111hinzc read/write bit 4 h half carry this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. bit 3 i interrupt mask this bit is set by hardware when entering in interrupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret instructions and is tested by the jrm and jrnm instructions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt rout ine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
central processing unit st7263bxx 30/186 doc id 7516 rev 8 stack pointer (sp) reset value: 017fh the stack pointer is a 16-bit register which is always pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 10 ). since the stack is 128 bytes deep, the 9 most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp6 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, without indicating the stack overflow. the previously stored information is then overwritten and therefore lost. the stack also wraps in case of an underflow. the stack is used to save the return address during a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instructions. in the case of an interrupt, the pcl is stored at the first location bit 2 n negative this bit is set and cleared by hardware. it is representative of the result sign of the last arithmetic, logical or data m anipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is nega tive (that is, the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instructions. bit 1 z zero this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last oper ation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 c carry/borrow this bit is set and cleared by hardware and software. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by th e ?bit test and branch?, shift and rotate instructions. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 sp6 sp5 sp4 sp3 sp2 sp1 sp0 read/write
st7263bxx central processing unit doc id 7516 rev 8 31/186 pointed to by the sp. then the other registers are stored in the next locations as shown in figure 10 . when an interrupt is received, the sp is decremented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an interrupt five locations in the stack area. figure 10. stack manipulation example figure 11. cpu registers pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 017fh @ 0100h stack higher address = 017fh stack lower address = 0100h accumulator x index register y index register stack pointer condition code register program counter 70 1c 1 1 hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
reset and clock management st7263bxx 32/186 doc id 7516 rev 8 6 reset and clock management 6.1 reset the reset procedure is used to provide an orderly software start-up or to exit low power modes. three reset modes are provided: a low voltage (lvd) reset, a watchdog reset and an external reset at the reset pin. a reset causes the reset vector to be fetched from addresses fffeh and ffffh in order to be loaded into the pc and with program execution starting from this point. an internal circuitry provides a 4096 cpu cloc k cycle delay from the time that the oscillator becomes active. caution: when the st7 is unprogrammed or fully erased , the flash is blank an d the reset vector is not programmed. for this reason, it is recommended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. 6.1.1 low voltage detector (lvd) low voltage reset circuitry generates a reset when v dd is: below v it+ when v dd is rising below v it- when v dd is falling during low voltage reset, the reset pin is held low, thus permitting the mcu to reset other devices. it is recommended to make sure that the v dd supply voltage rises monotonously when the device is exiting from reset, to ensure the application functions properly. 6.1.2 watchdog reset when a watchdog reset occurs, the reset pin is pulled low permitting the mcu to reset other devices in the same way as the low voltage reset ( figure 12 ). 6.1.3 external reset the external reset is an active low input signal applied to the reset pin of the mcu. as shown in figure 15 , the reset signal must stay low for a minimum of one and a half cpu clock cycles. an internal schmitt trigger at the reset pin is provided to improve noise immunity.
st7263bxx reset and clock management doc id 7516 rev 8 33/186 figure 12. low voltage detector functional diagram figure 13. low voltage reset signal output 1. hysteresis (v it+ -v it- ) = v hys figure 14. temporization timing diagram after an internal reset low voltage v dd from watchdog reset reset internal detector reset reset v dd v it+ v it- v dd addresses $fffe temporization (4096 cpu clock cycles) v it+
reset and clock management st7263bxx 34/186 doc id 7516 rev 8 figure 15. reset timing diagram 1. refer to electrical charac teristics for values of t ddr , t oxov , v it+ , v it- and v hys v dd oscin f cpu ffff fffe pc reset watchdog reset t ddr t oxov 4096 cpu clock cycles delay
st7263bxx reset and clock management doc id 7516 rev 8 35/186 6.2 clock system 6.2.1 general description the mcu accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. the internal clock (f cpu ) is derived from the external oscillator frequency (f osc ), which is divided by 3 (and by 2 or 4 for usb, depending on the external clock used). the internal clock is further divided by 2 by setting the sms bit in the miscellaneous register. using the osc24/12 bit in the option byte, a 12 mhz or a 24 mhz external clock can be used to provide an internal frequency of either 2, 4 or 8 mhz while maintaining a 6 mhz for the usb (refer to figure 18 ). the internal clock signal (f cpu ) is also routed to the on-chip peripherals. the cpu clock signal consists of a square wave with a duty cycle of 50%. the internal oscillator is designed to operate with an at-cut parallel resonant quartz or ceramic resonator in the frequency range specified for f osc . the circuit shown in figure 17 is recommended when using a crystal, and ta b l e 8 lists the recommended capacitance. the crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilization time. 6.2.2 external clock an external clock may be applied to the oscin input with the oscout pin not connected, as shown on figure 16 . the t oxov specifications do not apply when using an external clock input. the equivalent specification of the external clock source should be used instead of t oxov (see table 62: control timing characteristics ). figure 16. external clock source connections table 8. recommended values for 24 mhz crystal resonator recommended capacitance and resistance r smax (1) 1. r smax is the equivalent serial resistor of the crystal (see crys tal specification). 20 25 70 c oscin 56pf 47pf 22pf c oscout 56pf 47pf 22pf r p 1-10 m 1-10 m 1-10 m oscin oscout external clock nc
reset and clock management st7263bxx 36/186 doc id 7516 rev 8 figure 17. crystal/ceramic resonator figure 18. clock block diagram oscin oscout c oscin c oscout r p %3 cpu and 8, 4 or 2 mhz 6 mhz (usb) 24 or peripherals) %2 1 0 %2 12 mhz crystal %2 0 1 osc24/12 sms %2
st7263bxx interrupts doc id 7516 rev 8 37/186 7 interrupts the st7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in ta bl e 9 and a non-maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 19 . the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent additional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ta bl e 9 for vector addresses). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, a servicing interrupt cannot be interrupted because the i bit is set by hardware entering in interrupt routine. in the case several interrupts are simultaneously pending, a hardware priority defines which one will be serviced first (see ta bl e 9 ). non-maskable software interrupts this interrupt is entered when the trap instruction is executed regardless of the state of the i bit. it will be serviced a ccording to the flowchart on figure 19 . interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specific mentioned interrupts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in ta b l e 9 ). external interrupts the pins iti/pak and itj/pbk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising edge occurs on this pin. conversely, the itl/pan and itm/pbn pins (l=3,4; m= 7,8; n=6,7) can generate an interrupt when a falling edge occurs on this pin. interrupt generation will occur if it is enabled with the itie bit (i=1 to 8) in the itrfre register and if the i bit of the cc is reset.
interrupts st7263bxx 38/186 doc id 7516 rev 8 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by one of the two following operations: writing ?0? to the corresponding bit in the status register. accessing the status register while the flag is set followed by a read or write of an associated register. note: 1 the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting to be enabled) will therefore be lost if the clear sequenc e is executed. 2 all interrupts allow the processor to leave the wait low power mode. 3 exit from halt mode may only be triggered by an external interrupt on one of the iti ports (pa4-pa7 and pb4-pb7), an end suspend mode interrupt coming from usb peripheral, or a reset. figure 19. interrupt processing flowchart bit i set y n iret y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n
st7263bxx interrupts doc id 7516 rev 8 39/186 7.1 interrupt register (itrfre) address: 0008h reset value: 0000 0000 (00h) table 9. interrupt mapping n source block description register label priority order exit from halt vector address reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh flash flash start programming interrupt yes fffah-fffbh usb end suspend mode istr yes fff8h-fff9h 1 iti external interrupts itrfre fff6h-fff7h 2 timer timer peripheral interrupts timsr no fff4h-fff5h 3 i2c i2c peripheral interrupts i2csr1 fff2h-fff3h i2csr2 4 sci sci peripheral interrupts scisr fff0h-fff1h 5 usb usb peripheral interrupts istr ffeeh-ffefh 7 0 it8e it7e it6e it5e it4e it3e it2e it1e read/write [7:0] tie (i=1 to 8) . interrupt enable control bits . if an itie bit is set, the corresponding interrupt is generated when a rising edge occurs on the pin pa4/it1 or pa5/it2 or pb4/it5 or pb5/it6 or a falling edge occurs on the pin pa6/it3 or pa7/it4 or pb6/it7 or pb7/it8 no interrupt is generated elsewhere. note: analog input must be disabled for interrupts coming from port b.
power saving modes st7263bxx 40/186 doc id 7516 rev 8 8 power saving modes 8.1 introduction to give a large measure of flexibility to the ap plication in terms of power consumption, two main power saving modes are implemented in the st7. after a reset, the normal operating mode is selected by default (run mode). this mode drives the device (cpu and embedded periphera ls) by means of a master clock which is based on the main oscillato r frequency divided by 3 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instructi on whose action depends on the oscillator status. 8.2 halt mode the mcu consumes the least amount of power in halt mode. the halt mode is entered by executing the halt instruction. the internal osc illator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. when entering halt mode, the i bit in the condition code register is cleared. thus, all external interrupts (iti or usb end suspend mode) are allowed and if an interrupt occurs, the cpu clock becomes active. the mcu can exit halt mode on reception of either an external interrupt on iti, an end suspend mode interrupt coming from usb peripheral, or a re set. the oscillator is then turned on and a stabilization time is provided before re leasing cpu operation. the stabilization time is 4096 cpu clock cycles. after the start up delay, the cpu continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.
st7263bxx power saving modes doc id 7516 rev 8 41/186 figure 20. halt mode flowchart 1. before servicing an interrupt, the cc register is pus hed on the stack. the i-bit is set during the interrupt routine and cleared when the cc register is popped. 8.3 slow mode in slow mode, the oscillator freq uency can be divided by 2 as selected by the sms bit in the miscellaneous register. the cpu and peripherals are clocked at this lower frequency. slow mode is used to reduce power consumption, and enables the user to adapt the clock frequency to the available supply voltage. 8.4 wait mode wait mode places the mcu in a low power consumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? st7 software instruction. all peripherals remain active. duri ng wait mode, the i bit of the cc register is forced to 0 to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. n n external interrupt* reset halt instruction 4096 cpu clock fetch reset vector or service interrupt cycles delay cpu clock oscillator periph. clock i-bit on on set on cpu clock oscillator periph. clock i-bit off off cleared off y y
power saving modes st7263bxx 42/186 doc id 7516 rev 8 the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 21 . related documentation an 980: st7 keypad decoding techniques, implementing wakeup on keystroke an1014: how to minimize the st7 power consumption an1605: using an active rc to wakeup the st7lite0 from power saving mode figure 21. wait mode flowchart 1. before servicing an interrupt, the cc register is pus hed on the stack. the i-bit is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu clock oscillator periph. clock i-bit on on cleared off cpu clock oscillator periph. clock i-bit on on set on fetch reset vector or service interrupt 4096 cpu clock cycles delay if reset
st7263bxx i/o ports doc id 7516 rev 8 43/186 9 i/o ports 9.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins analog signal input (adc) alternate signal input/output for the on-chip peripherals external interrupt generation an i/o port consists of up to 8 pins. each pin can be programmed independently as a digital input (with or without interrupt generation) or a digital output. 9.2 functional description each port is associated to 2 main registers: data register (dr) data direction register (ddr) each i/o pin may be programmed using the corr esponding register bits in ddr register: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. note: 1 all the inputs are trig gered by a schmitt trigger. 2 when switching from input mode to output mode, the dr register should be written first to output the correct value as soon as the port is configured as an output. interrupt function when an i/o is configured as an input with interrupt, an event on this i/o can generate an external interrupt request to the cpu. the interrupt sensitivity is given independently according to the description mentioned in the itrfre interrupt register. each pin can independently generate an interrupt request. each external interrupt vector is linked to a dedicated group of i/o port pins (see interrupts section). if more than one input pin is selected simultaneously as an interrupt source, this is logically ored. for this reason if one of the in terrupt pins is tied low, the other ones are masked. table 10. i/o pin functions ddr mode 0 input 1 output
i/o ports st7263bxx 44/186 doc id 7516 rev 8 output mode the pin is configured in output mode by se tting the corresponding ddr register bit (see table 7). in this mode, writing ?0? or ?1? to the dr regi ster applies this digital value to the i/o pin through the latch. therefore, the previously saved value is restored when the dr register is read. note: the interrupt function is disabled in this mode. digital alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. this alternate function takes priority over standard i/o programming. when the signal is coming from an on-chip peripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pin?s state is also digi tally readable by addressing the dr register. note: 1 input pull-up configuration can cause an unexpected value at the input of the alternate peripheral input. 2 when the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (ddr = 0). caution: the alternate function must not be activated as l ong as the pin is configured as an input with interrupt in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input the i/o must be configured as a floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected analog pin. warning: the analog input voltage level must be within the limits stated in the absolute maximum ratings.
st7263bxx i/o ports doc id 7516 rev 8 45/186 9.3 i/o port implementation the hardware implementation on each i/o port depends on the settings in the ddr register and specific feature of the i/o port such as adc input or true open drain. 9.3.1 port a figure 22. pa0, pa3, pa4, pa5, pa6, pa7 and pd[7:4] configuration table 11. port a0, a3, a4, a5, a6, a7 description port a i/os alternate function input (1) 1. reset state. output signal condition pa0 with pull-up push-pull mco (main clock output) mco = 1 (miscr) pa3 with pull-up push-pull timer extclk cc1 =1 cc0 = 1 (timer cr2) pa4 with pull-up push-pull timer icap1 it1 schmitt triggered input it1e = 1 (itifre) pa5 with pull-up push-pull timer icap2 it2 schmitt triggered input it2e = 1 (itifre) pa 6 (2) 2. not available on so24 with pull-up push-pull timer ocmp1 oc1e = 1 it3 schmitt triggered input it3e = 1 (itifre) pa7 with pull-up push-pull timer ocmp2 oc2e = 1 it4 schmitt triggered input it4e = 1 (itifre) dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up output p-buffer n-buffer 1 0 1 0 cmos schmitt trigger v ss v dd diodes data bus
i/o ports st7263bxx 46/186 doc id 7516 rev 8 figure 23. pa1, pa2 configuration table 12. pa1, pa2 description (1) port a i / o alternate function input 1 output signal condition pa1 without pull-up very high current open drain sda (i2c data) i2c enable pa2 without pull-up very high current open drain scl (i2c clock) i2c enable 1. reset state. ddr latch latch dr sel ddr sel pa d alternate enable n-buffer 1 0 cmos schmitt trigger v ss data bus
st7263bxx i/o ports doc id 7516 rev 8 47/186 9.3.2 port b table 13. port b description port b i/o alternate function input (1) output signal condition pb0 without pull-up push-pull analog input (adc) ch[3:0] = 000 (adccsr) pb1 without pull-up push-pull analog input (adc) ch[3:0] = 001 (adccsr) usboe (usb output enable) (2) usboe =1 (miscr) pb2 without pull-up push-pull analog input (adc) ch[3:0]= 010 (adccsr) pb3 without pull-up push-pull analog input (adc) ch[3:0]= 011 (adccsr) pb4 without pull-up push-pull analog input (adc) ch[3:0]= 100 (adccsr) it5 schmitt triggered input it5e = 1 (itifre) pb5 without pull-up push-pull analog input (adc) ch[3:0]= 101 (adccsr) it6 schmitt triggered input it6e = 1 (itifre) pb6 without pull-up push-pull analog input (adc) ch[3:0]= 110 (adccsr) it7 schmitt triggered input it7e = 1 (itifre) pb7 without pull-up push-pull analog input (adc) ch[3:0]= 111 (adccsr) it8 schmitt triggered input it8e = 1 (itifre) 1. reset state 2. on so24 only
i/o ports st7263bxx 48/186 doc id 7516 rev 8 figure 24. port b and d[3:0] configuration dr ddr latch latch dr sel ddr sel v dd pa d analog switch analog enable (adc) alternate enable alternate enable digital enable alternate enable alternate alternate input output p-buffer n-buffer 1 0 1 0 v ss data bus common analog rail v dd diodes
st7263bxx i/o ports doc id 7516 rev 8 49/186 9.3.3 port c figure 25. port c configuration table 14. port c description port c i / o alternate function input (1) output signal condition pc0 with pull-up push-pull rdi (sci input) pc1 with pull-up push-pull tdo (sci output) sci enable pc2 (2) with pull-up push-pull usboe (usb output enable) usboe =1 (miscr) 1. reset state 2. not available on so24 dr ddr latch latch dr sel ddr sel v dd pa d alternate enable alternate enable alternate enable alternate alternate input pull-up output p-buffer n-buffer 0 1 0 cmos schmitt trigger v ss v dd data bus diodes
i/o ports st7263bxx 50/186 doc id 7516 rev 8 9.3.4 port d 9.3.5 register description data registers (pxdr) address port a data register (padr): 0000h port b data register (pbdr): 0002h port c data register (pcdr): 0004h port d data register (pddr): 0006h reset value port a: 0000 0000 (00h) port b: 0000 0000 (00h) port c: 1111 x000 (fxh) port d: 0000 0000 (00h) note: for port c, unused bits (7-3) are not accessible. the dr register has a specific behavior according to the selected input/output configuration. writing the dr register is always taken into account even if the pin is configured as an input. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). note: when using open-drain i/os in output configuration, the value read in dr is the digital value applied to the i/opin. table 15. port d description port d i / o alternate function input (1) output signal condition pd0 without pull-up push-pull analog input (adc) ch[3:0] = 1000 (adccsr) pd1 without pull-up push-pull analog input (adc) ch[3:0] = 1001 (adccsr) pd2 without pull-up push-pull analog input (adc) ch[3:0] = 1010 (adccsr) pd3 without pull-up push-pull analog input (adc) ch[3:0] = 1011 (adccsr) pd4 with pull-up push-pull pd5 with pull-up push-pull pd6 with pull-up push-pull pd7 with pull-up push-pull 1. reset state
st7263bxx i/o ports doc id 7516 rev 8 51/186 . data direction register (pxddr) address port a data direction register (paddr): 0001h port b data direction register (pbddr): 0003h port c data direction register (pcddr): 0005h port d data direction register (pdddr): 0007h reset value port a: 0000 0000 (00h) port b: 0000 0000 (00h) port c: 1111 x000 (fxh) port d: 0000 0000 (00h) note: for port c, unused bits (7-3) are not accessible . 7 0 d7 d6 d5 d4 d3 d2 d1 d0 read/write [7:0] d[7:0] data register 8 bits. 7 0 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 read/write [7:0]d d[7:0] data direction register 8 bits. the ddr register gives the input/output direct ion configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode table 16. i/o ports register map address (hex.) register label 76543210 00 padr msb lsb 01 paddr msb lsb 02 pbdr msb lsb 03 pbddr msb lsb 04 pcdr msb lsb 05 pcddr msb lsb 06 pddr msb lsb 07 pdddr msb lsb
i/o ports st7263bxx 52/186 doc id 7516 rev 8 9.3.6 related documentation an1045: s/w implementation of i 2 c bus master an1048: software lcd driver
st7263bxx miscellaneous register doc id 7516 rev 8 53/186 10 miscellaneous register miscellaneous register (miscr) address: 0009h reset value: 0000 0000 (00h) 7 0 -----smsusboemco read/write [7:3] reserved 2 sms slow mode select . this bit is set by software and only cleared by hardware after a reset. if this bit is set, it enables the use of an internal divide-by-2 clock divider (refer to figure 18 on page 36 ). the sms bit has no effect on the usb frequency. 0: divide-by-2 disabled and cpu clock frequency is standard 1: divide-by-2 enabled and cpu clock frequency is halved. 1 usboe usb enable. if this bit is set, the port pc2 (pb1 on so24) outputs the usb output enable signal (at ?1? when the st7 usb is transmitting data). unused bits 7-4 are set. 0 mco main clock out selection this bit enables the mco alternate function on the pa0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f cpu on i/o port)
on-chip peripherals st7263bxx 54/186 doc id 7516 rev 8 11 on-chip peripherals 11.1 watchdog timer (wdg) 11.1.1 introduction the watchdog timer is used to detect the oc currence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset on expiry of a programmed time period, unless the program refreshes the counter?s contents before the t6 bit becomes cleared. 11.1.2 main features programmable free-runni ng counter (64 increments of 49,152 cpu cycles) programmable reset reset (if watchdog activated) when the t6 bit reaches zero optional reset on halt instruction (configurable by option byte) hardware watchdog selectable by option byte. 11.1.3 functional description the counter value stored in the cr register (bits t6:t0), is decremented every 49,152 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t6:t0) rolls over from 40h to 3fh (t 6 becomes cleared), it initiates a reset cycle by driving low the reset pin for t w(rstl)out (see ta bl e 7 2 ). the application program must write in the cr register at regular intervals during normal operation to prevent an mcu reset. this down counter is free-running: it counts down even if the watchdog is disabled. the value to be stored in the cr register must be between ffh and c0h (see ta b l e 1 7 ): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an immediate reset the t5:t0 bits contain the number of increments which represents the time delay before the watchdog produces a reset.
st7263bxx on-chip peripherals doc id 7516 rev 8 55/186 figure 26. watchdog block diagram a note: following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). 11.1.4 software watchdog option if software watchdog is selected by option byte, the watchdog is disabled following a reset. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). 11.1.5 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. 11.1.6 low power modes wait instruction no effect on watchdog. table 17. watchdog timing (f cpu = 8 mhz) cr register initial value wdg timeout period (ms) max ffh 393.216 min c0h 6.144 reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 49152 t1 t2 t3 t4 t5
on-chip peripherals st7263bxx 56/186 doc id 7516 rev 8 halt instruction if the watchdog reset on halt option is selected by option byte, a halt instruction causes an immediate reset generation if the watchdog is activated (wdga bit is set). using halt mode with the wdg (option) if the watchdog reset on halt option is not selected by option byte, the halt mode can be used when the watchdog is enabled. in this case, the halt instruction stops the os cillator. when the osc illator is stopped, the wdg stops counting and is no longer able to generate a reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg restarts counting after 4096 cpu clocks. if a reset is generated, the wdg is disabled (reset state). recommendations: make sure that an external event is available to wake up the microcontroller from halt mode. before executing the halt instruction, refresh the wdg counter, to avoid an unexpected wdg reset immediately after waking up the microcontroller. when using an external interrupt to wake up the microcontroller, reinitialize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to external interference or by an unforeseen logical condition. for the same reason, reinitialize the level sens itiveness of each external interrupt as a precautionary measure. the opcode for the halt instruction is 0x8e . to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memory. for example, avoid defining a constant in rom with the value 0x8e. as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt). 11.1.7 interrupts none.
st7263bxx on-chip peripherals doc id 7516 rev 8 57/186 11.1.8 register description control register (cr) reset value: 0111 1111 (7fh) 7 0 wdga t6 t5 t4 t3 t2 t1 t0 read/write 7 wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled [6:0] t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). table 18. watchdog timer register map and reset values address (hex.) register label 765 4 3210 0ch wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
on-chip peripherals st7263bxx 58/186 doc id 7516 rev 8 11.2 16-bit timer 11.2.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input signals ( input capture ) or generation of up to two output waveforms ( output compare and pwm ). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequencies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 11.2.2 main features programmable prescaler: f cpu divided by 2, 4 or 8 overflow status flag and maskable interrupt external clock input (must be at least four times slower than the cpu clock speed) with the choice of active edge 1 or 2 output compare functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated programmable signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt 1 or 2 input capture functions each with: ? 2 dedicated 16-bit registers ? 2 dedicated active edge selection signals ? 2 dedicated status flags ? 1 dedicated maskable interrupt pulse width modulation mode (pwm) one pulse mode reduced power mode 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 27 . note: some timer pins may not be available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signa l on a non-bonded pi n, the value will always be ?1?.
st7263bxx on-chip peripherals doc id 7516 rev 8 59/186 11.2.3 functional description counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high and low. counter register (cr) counter high register (chr) is t he most significant byte (msb). counter low register (clr) is the least significant byte (lsb). alternate counter register (acr) alternate counter high register (achr) is the m ost significant byte (msb) . alternate counter low register (aclr) is the least significant byte (lsb). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit timer). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bi ts of the cr2 register, as illustrated in ta bl e 2 4 . the value in the counter register repeats every 131072, 262144 or 524288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
on-chip peripherals st7263bxx 60/186 doc id 7516 rev 8 figure 27. timer block diagram 1. if ic, oc and to interrupt requests have separate ve ctors then the last or is not present (see device interrupt vector table). mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 timd 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (control/status register) 6 16 8 8 8 8 8 8 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register (see note) csr
st7263bxx on-chip peripherals doc id 7516 rev 8 61/186 figure 28. 16-bit read sequence (from either the counter register or the alternate counter register) the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they return the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, output compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: ? toie bit of the cr1 register is set and ? i bit of the cc register is cleared. if one of these conditions is false, the interr upt remains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. note: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). external clock the external clock (where available) is selected if cc0 = 1 and cc1 = 1 in the cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the external clock pin extclk that will trigger the free running counter. the counter is synchronize d with the falling edge of the internal cpu clock. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte
on-chip peripherals st7263bxx 62/186 doc id 7516 rev 8 a minimum of four falling edges of the cpu clock must occur betw een two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the cpu clock frequency. figure 29. counter timing diagram, internal clock divided by 2 1. the mcu is in reset state when the internal rese t signal is high, when it is low the mcu is running. figure 30. counter timing diagram, internal clock divided by 4 1. the mcu is in reset state when the internal rese t signal is high, when it is low the mcu is running. figure 31. counter timing diagram, internal clock divided by 8 1. the mcu is in reset state when the internal rese t signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st7263bxx on-chip peripherals doc id 7516 rev 8 63/186 input capture in this section, the index, i , may be 1 or 2 because there are two input capture functions in the 16-bit timer. the two 16-bit input capture registers (ic1r and ic2r) are used to latch the value of the free running counter after a transition is detected on the icap i pin (see figure 32 ). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure to use the input capture function select the following in the cr2 register: 1. select the timer clock (cc[1:0]) (see ta bl e 2 4 ). 2. select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input or input with pull-up without interrupt if this configuration is available). 3. select the following in the cr1 register: a) set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin b) select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input or input with pull-up without interrupt if this config uration is available). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 33 ). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. otherwise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. table 19. ic/r register ms byte ls byte icir ic i hr ic i lr
on-chip peripherals st7263bxx 64/186 doc id 7516 rev 8 note: 1 after reading the icihr regist er, transfer of input capture data is inhibited and icfi will never be set until the icilr re gister is also read. 2 the icir register contains the free running counter value which corresponds to the most recent input capture. 3 the two input capture functions can be used together even if the timer also uses the two output compare functions. 4 in one pulse mode and pwm mode only input capture 2 can be used. 5 the alternate inputs (icap1 and icap2) are always directly connected to the timer. so any transitions on these pins activates the input capture function. moreover if one of the icapi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the icie bit is set. this can be avoided if the input capture function i is disabled by reading the icihr (see note 1). 6 the tof bit can be used with interrupt generation in order to measure events that go beyond the timer range (ffffh). figure 32. input capture block diagram figure 33. input capture timing diagram 1. the rising edge is the active edge. icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register
st7263bxx on-chip peripherals doc id 7516 rev 8 65/186 output compare in this section, the index, i , may be 1 or 2 because there are two output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output compare register and the free running counter, the output compare function: assigns pins with a programmable value if the oc i e bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure to use the output compare function, select the following in the cr2 register: 1. set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. 2. select the timer clock (cc[1:0]) (see ta bl e 2 4 ). 3. select the following in the cr1 register: a) select the olvl i bit to applied to the ocmp i pins after the match occurs. b) set the ocie bit to generate an interrupt if it is needed. when a match is found between oc i r register and cr register: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr1 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) table 20. oc/r register ms byte ls byte oc i roc i hr oc i lr oc i r = t * f cpu presc
on-chip peripherals st7263bxx 66/186 doc id 7516 rev 8 presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see ta b l e 2 4 ) if the timer clock is an external clock, the formula is: where: t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (that is, clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to prevent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). note: 1 after a processor write cycle to the ocihr r egister, the output compar e function is inhibited until the ocilr register is also written. 2 if the ocie bit is not set, the ocmpi pin is a general i/o port and the olvli bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3 in both internal and external clock modes, ocfi and ocmpi are set while the counter value equals the ocir register value (see figure 35 on page 67 for an example with f cpu /2 and figure 36 on page 67 for an example with f cpu /4). this behavior is the same in opm or pwm mode. 4 the output compare functions can be used both for generating external events on the ocmpi pins even if the input capture mode is also used. 5 the value in the 16-bit oc i r register and the olvi bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit = 1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. the folvl i bits have no effect in both one pulse mode and pwm mode. oc i r = t * f ext
st7263bxx on-chip peripherals doc id 7516 rev 8 67/186 figure 34. output compare block diagram figure 35. output compare timing diagram, f timer =f cpu /2 figure 36. output compare timing diagram, f timer =f cpu /4 output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf output compare flag i (ocf i ) ocmp i pin (olvl i =1)
on-chip peripherals st7263bxx 68/186 doc id 7516 rev 8 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure to use one pulse mode: 1. load the oc1r register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after the pulse. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin during the pulse. ? select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: ? set the oc1e bit, the ocmp1 pin is then dedicated to the output compare 1 function. ? set the opm bit. ? select the timer clock cc[1:0] (see ta bl e 2 4 ). figure 37. one pulse mode cycle then, on a valid event on the icap1 pin, the counter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the value fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (that is, clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 ocmp1 = olvl2 counter is reset to fffch icf1 bit is set icr1 = counter
st7263bxx on-chip peripherals doc id 7516 rev 8 69/186 the oc1r register value required for a specif ic timing application can be calculated using the following formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on the cc[1:0] bits, see ta b l e 2 4 ) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 38 ). note: 1 the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3 if olvl1 = olvl2 a continuous sig nal will be seen on the ocmp1 pin. 4 the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5 when one pulse mode is used oc1r is dedicated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. figure 38. one pulse mode timing example 1. iedg1 = 1, oc1r = 2ed0h, olvl1 = 0, olvl2 = 1 oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5 counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 01f8 01f8 2ed3 ic1r
on-chip peripherals st7263bxx 70/186 doc id 7516 rev 8 figure 39. pulse width modulation mode timing with 2 output compare functions 1. oc1r = 2ed0h, oc2r = 34e2, olvl1 = 0, olvl2 = 1 on timers with only one output compare register, a fixed frequency pwm signal can be generated using the output compare and the counter overflow to define the pulse length. pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. pulse width modulation mode uses the complete output compare 1 function plus the oc2r register, and so this functionality can no t be used when pwm mode is activated. in pwm mode, double buffering is implemented on the output compare registers. any new values written in the oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2) to avoid spikes on the pwm output pin (ocmp1). procedure to use pulse width modulation mode: 1. load the oc2r register with the value corresponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corresponding to the period of the pulse if (olvl1 = 0 and olvl2 = 1) using the formula in the opposite column. 3. select the following in the cr1 register: ? using the olvl1 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc1r register. ? using the olvl2 bit, select the level to be applied to the ocmp1 pin after a successful comparison with the oc2r register. 4. select the following in the cr2 register: ? set oc1e bit: the ocmp1 pin is then dedicated to the output compare 1 function. ? set the pwm bit. ? select the timer clock (cc[1:0]) (see ta bl e 2 4 ). counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 fffc fffd fffe 2ed0 2ed1 2ed2
st7263bxx on-chip peripherals doc id 7516 rev 8 71/186 figure 40. pulse width modulation cycle if olvl1 = 1 and olvl2 = 0 the length of the positive pulse is the difference between the oc2r and oc1r registers. if olvl1 = olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific timing application can be calculated using the following formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depending on cc[1:0] bits, see ta bl e 2 4 ) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 39 ) note: 1 after a write instruction to the ocihr register, the output co mpare function is inhibited until the ocilr register is also written. 2 the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3 the icf1 bit is set by hardware when the c ounter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4 in pwm mode the icap1 pin can not be used to perform input capture because it is disconnected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5 when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc - 5 oc i r = t * f ext -5
on-chip peripherals st7263bxx 72/186 doc id 7516 rev 8 11.2.4 low power modes a 11.2.5 interrupts the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc regi ster is reset (r im instruction). 11.2.6 summary of timer modes table 21. low power modes mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with ?exit from halt mode? capability or from the counter reset val ue when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequently, when the mcu is woken up by an interrupt with ?exit from halt mode? capability, the icf i bit is set, and the counter valu e present when exiting from halt mode is captured into the ic i r register. table 22. interrupts interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie ye s n o input capture 2 event icf2 output compare 1 event (not available in pwm mode) ocf1 ocie output compare 2 event (not available in pwm mode) ocf2 timer overflow event tof toie table 23. summary of timer modes modes timer resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) ye s ye s ye s ye s output compare (1 and/or 2) one pulse mode no not recommended (1) 1. see note 4 in section : one pulse mode . no partially (2) 2. see note 5 in section : one pulse mode . pwm mode not recommended (3) 3. see note 4 in section : pulse width modulation mode . no
st7263bxx on-chip peripherals doc id 7516 rev 8 73/186 11.2.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. control register 1 (cr1) reset value: 0000 0000 (00h) 7 0 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1 read/write 7 icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. 6 ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. 5 toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. 4 folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1:forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. 3 folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no successful comparison. 2 olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r register and ocxe is set in the cr2 register. this value is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. 1 iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. 0 olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin whenever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register.
on-chip peripherals st7263bxx 74/186 doc id 7516 rev 8 control register 2 (cr2) reset value: 0000 0000 (00h) 7 0 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg read/write 7 oc1e output compare 1 pin enable. this bit is used only to output the si gnal from the timer on the ocmp1 pin (olv1 in output compare mode, both olv1 an d olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, th e output compare 1 function of the timer remains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. 6 oc2e output compare 2 pin enable. this bit is used only to output the si gnal from the timer on the ocmp2 pin (olv2 in output compare mode). whatever t he value of the oc2e bit, the output compare 2 function of the timer remains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. 5 opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the cont ents of the oc1r register. 4 pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse dep ends on the value of oc1r register; the period depends on the value of oc2r register. [3:2] cc[1:0] clock control. the timer clock mode depends on these bits (see ta b l e 2 4 ). if the external clock pin is not available, programming the external clock configuration stops the counter. 1 iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. 0 exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register.
st7263bxx on-chip peripherals doc id 7516 rev 8 75/186 control/status register (csr) reset value: xxxx x0xx (xxh) table 24. clock control bits timer clock cc1 cc0 f cpu / 4 0 0 f cpu / 2 1 f cpu / 8 1 0 external clock (where available) 1 76543 0 icf1 ocf1 tof icf2 ocf2 timd 0 0 read only read/write 7 icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. 6 ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counte r has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) register. 5 tof timer overflow flag. 0: no timer overflow (reset value). 1:the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr register, then read or writ e the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. 4 icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register.
on-chip peripherals st7263bxx 76/186 doc id 7516 rev 8 input capture 1 high register (ic1hr) reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). output compare 1 high register (oc1hr) reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 3 ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counte r has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) register. 2 timd timer disable. this bit is set and cleared by software. when set, it freezes the timer prescaler and counter and disabled the output function s (ocmp1 and ocmp2 pins) to reduce power consumption. access to the timer re gisters is still available, allowing the timer configuration to be changed, or the counter reset, while it is disabled. 0: timer enabled 1: timer prescaler, counter and outputs disabled [1:0] reserved, must be kept cleared. 7 0 msb lsb read only 7 0 msb lsb read only 7 0 msb lsb read/write
st7263bxx on-chip peripherals doc id 7516 rev 8 77/186 output compare 2 high register (oc2hr) reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the csr register clears the tof bit. alternate counter high register (achr) reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. 7 0 msb lsb read/write 7 0 msb lsb read/write 7 0 msb lsb read/write 7 0 msb lsb read only 7 0 msb lsb read only
on-chip peripherals st7263bxx 78/186 doc id 7516 rev 8 alternate counter low register (aclr) reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to csr register does not clear the tof bit in the csr register. input capture 2 high register (ic2hr) reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 2 event). 7 0 msb lsb read only 7 0 msb lsb read only 7 0 msb lsb read only 7 0 msb lsb read only
st7263bxx on-chip peripherals doc id 7516 rev 8 79/186 table 25. 16-bit timer register map and reset values address (hex.) register label 76543210 11 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 12 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 13 csr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 timd 0 0 0 0 0 14 ic1hr reset value msb lsb 15 ic1lr reset value msb lsb 16 oc1hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 17 oc1lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 18 chr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 1 lsb 1 19 clr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 0 lsb 0 1a achr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 1 lsb 1 1b aclr reset value msb 1 - 1 - 1 - 1 - 1 - 1 - 0 lsb 0 1c ic2hr reset value msb lsb 1d ic2lr reset value msb lsb 1e oc2hr reset value msb 1 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0 1f oc2lr reset value msb 0 - 0 - 0 - 0 - 0 - 0 - 0 lsb 0
on-chip peripherals st7263bxx 80/186 doc id 7516 rev 8 11.3 serial communicat ions interface (sci) 11.3.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci offers a very wide range of baud rates using two baud rate generator systems. 11.3.2 main features full duplex, asynchronous communications nrz standard format (mark/space) independently programmable transmit and receive baud rates up to 250k baud. programmable data word length (8 or 9 bits) receive buffer full, transmit buffer empty and end of transmission flags two receiver wakeup modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations separate enable bits for transmitter and receiver four error detection flags: ? overrun error ? noise error ?frame error ? parity error six interrupt sources with flags: ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error detected ? parity error parity control: ? transmits parity bit ? checks parity of received data byte reduced power consumption mode 11.3.3 general description the interface is externally connected to another device by two pins (see figure 42 ): tdo: transmit data output. when the transmitter and the receiver are disabled, the output pin returns to its i/o port configuration. when the transmitter and/or the receiver are enabled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.
st7263bxx on-chip peripherals doc id 7516 rev 8 81/186 through these pins, serial data is transmitted and received as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete. this interface uses two types of baud rate generator: a conventional type for commonly-used baud rates. figure 41. sci block diagram wake up unit receiver control sr transmit control tdre tc rdrf idle or nf fe pe sci control interrupt cr1 r8 t8 scid m wake pce ps pie received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data register) dr transmitter clock receiver clock receiver rate transmitter rate brr scp1 f cpu control control scp0 sct2 sct1 sct0 scr2 scr1scr0 /pr /16 baud rate generator sbk rwu re te ilie rie tcie tie cr2
on-chip peripherals st7263bxx 82/186 doc id 7516 rev 8 11.3.4 functional description the block diagram of the serial control interface, is shown in figure 41 it contains 6 dedicated registers: two control registers (scicr1 & scicr2) a status register (scisr) a baud rate register (scibrr) refer to the register descriptions in section 11.3.7 for the definitions of each bit. serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the scicr1 register (see figure 41 ). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data. a break character is interpreted on receiving ?0?s for some multiple of the frame period. at the end of the last break frame the transmitter inserts an extra ?1? bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 42. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra ?1? data frame break frame start bit extra ?1? data frame next data frame next data frame
st7263bxx on-chip peripherals doc id 7516 rev 8 83/186 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the scicr1 register. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the scidr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 41 ). procedure 1. select the m bit to define the word length. 2. select the desired baud rate using the scibrr and the scietpr registers. 3. set the te bit to assign the tdo pin to the alternate function and to send a idle frame as first transmission. 4. access the scisr register and write the data to send in the scidr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the scidr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the cc register. when a transmission is taking place, a write instruction to the scidr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the scidr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the cc register. clearing the tc bit is performed by the following software sequence: 1. an access to the scisr register 2. a write to the scidr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shi ft register with a br eak character. the break frame length depends on the m bit (see figure 42 ).
on-chip peripherals st7263bxx 84/186 doc id 7516 rev 8 as long as the sbk bit is set, the sci send br eak frames to the tdo pi n. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a transmission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the scidr. receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the scicr1 register. character reception during a sci reception, data shifts in least significant bit first through the rdi pin. in this mode, the scidr register consists or a buffer (rdr) between the internal bus and the received shift register (see figure 41 ). procedure 1. select the m bit to define the word length. 2. select the desired baud rate using the scibrr and the scierpr registers. 3. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is se t and the i bit is cleared in the cc register. the error flags can be set if a frame error, noise or an overrun error has been detected during reception. clearing the rdrf bit is performed by th e following software sequence done by: 1. an access to the scisr register 2. a read to the scidr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the sci handles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ilie bit is set and the i bit is cleared in the cc register. overrun error an overrun error occurs when a character is received when rdrf has not been reset. data can not be transferred from the sh ift register to the rdr register as long as the rdrf bit is not cleared.
st7263bxx on-chip peripherals doc id 7516 rev 8 85/186 when a overrun error occurs: the or bit is set. the rdr content will not be lost. the shift register will be overwritten. an interrupt is generated if the rie bit is se t and the i bit is cleared in the cc register. the or bit is reset by an access to the scisr register followed by a scidr register read operation. noise error oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have the same bit value, otherwise the nf flag is set. in the case of start bit detection, the nf flag is set on the basis of an algorithm combining both valid edge detection and three samples (8th, 9th, 10th). therefore, to prevent the nf flag getting set during start bit reception, there should be a valid edge detection as well as three valid samples. when noise is detected in a frame: the nf flag is set at the rising edge of the rdrf bit. data is transferred from the shift register to the scidr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf flag is reset by a scisr register read operation followed by a scidr register read operation. during reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are 011,101,110), the frame is discarded and the receiving sequence is not started for this frame. there is no rdrf bit set for this fram e and the nf flag is set internally (not accessible to the user). this nf flag is acce ssible along with the rdrf bit when a next valid frame is received. note: if the application start bit is not long enough to match the above requirements, then the nf flag may get set due to the short start bit. in this case, the nf flag may be ignored by the application software when the first valid byte is received. see also section . framing error a framing error is detected when: ? the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. ? a break is received. when the framing error is detected: ? the fe bit is set by hardware ? data is transferred from the shift register to the scidr register. ? no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a scisr register read operation followed by a scidr register read operation.
on-chip peripherals st7263bxx 86/186 doc id 7516 rev 8 baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp[1:0] bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct[2:0] bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr[2:0] bits) all these bits are in the scibrr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 38400 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is enabled. receiver muting and wakeup feature in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupts are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. receiver wakes-up by idle li ne detection when the receive line has recognized an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a ?1? as the most significant bit of a word, thus indicating that the message is an address. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. caution: in mute mode, do not write to the scicr2 register. if the sci is in mute mode during the read operation (rwu=1) and a address mark wake up event occurs (rwu is reset) before the write operation, the rwu bi t will be set again by this writ e operation. co nsequently the address byte is lost and the sci is not woken up from mute mode. tx = (16 * pr) * tr f cpu rx = (16 * pr) * rr f cpu
st7263bxx on-chip peripherals doc id 7516 rev 8 87/186 parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the scicr1 register. depending on the frame length defined by the m bit, the possible sci frame formats are as listed in ta bl e 2 6 . note: in case of wakeup by an address mark, the msb bit of the data is taken into account and not the parity bit even parity: the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit = 0). odd parity: the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit = 1). transmission mode: if the pce bit is set then the msb bit of the data written in the data register is not transmitted but is changed by the parity bit. reception mode: if the pce bit is set then the interface checks if the received data byte has an even number of ?1s? if even parity is selected (ps=0) or an odd number of ?1s? if odd parity is selected (ps=1). if the parity check fails, the pe flag is set in the scisr register and an interrupt is generated if pie is set in the scicr1 register. sci clock tolerance during reception, each bit is sampled 16 times. the majority of the 8th, 9th and 10th samples is considered as the bit value. for a valid bit detection, all the three samples should have the same value otherwise the noise flag (nf) is set. for example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be ?1?, but the noise flag bit is be set because the three samples values are not the same. consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. this means the clock frequency should not vary more than 6/16 (37.5%) within one bit. the sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. note: the internal samp ling clock of the microcontroller sa mples the pin value on every falling edge. therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. for example: if the baud rate is 15.625 kbaud (bit length is 64s), then the 8th, 9th and 10th samples will be at 28s, 32 s & 36 s respectively (the first sample starting ideally at 0 s). but if the falling edge of the internal table 26. frame formats (1) 1. sb = start bit, stb = stop bit, pb = parity bit m bit pce bit sci frame 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb |
on-chip peripherals st7263bxx 88/186 doc id 7516 rev 8 clock occurs just before the pin value change s, the samples would then be out of sync by ~4 s. this means the entire bit length must be at least 40 s (36 s for the 10th sample + 4 s for synchronization with the internal sampling clock). clock deviation causes the causes which contribute to the total deviation are: d tra : deviation due to transmitte r error (local oscillator erro r of the transmitter or the transmitter is transmitting at a different baud rate). d quant : error due to the baud rate quantisation of the receiver. d rec : deviation of the local oscillator of the receiver: this deviat ion can occur during the reception of one complete sci message assuming that the deviation has been compensated at the beginning of the message. d tcl : deviation due to the transmission line (generally due to the transceivers) all the deviations of the system should be added and compared to the sci clock tolerance: d tra + d quant + d rec + d tcl < 3.75% noise error causes see also description of noise error in section . start bit the noise flag (nf) is set during start bit reception if one of the following conditions occurs: 1. a valid falling edge is not de tected. a falling edge is consi dered to be valid if the 3 consecutive samples before the falling edge occu rs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a ?1?. 2. during sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a ?1?. therefore, a valid start bit must satisfy both the above conditions to prevent the noise flag getting set. data bits the noise flag (nf) is set during normal data bit reception if the following condition occurs: during the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. the majority of the 8th, 9th and 10th samples is considered as the bit value. therefore, a valid data bit must have samples 8, 9 and 10 at the same value to prevent the noise flag getting set.
st7263bxx on-chip peripherals doc id 7516 rev 8 89/186 figure 43. bit sampling in reception mode 11.3.5 low power modes 11.3.6 interrupts the sci interrupt events are connected to the same interrupt vector. these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). rdi line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 table 27. low power modes mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitti ng/receiving until halt mode is exited. table 28. interrupts interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie ye s n o overrun error detected or yes no idle line detected idle ilie yes no parity error pe pie yes no
on-chip peripherals st7263bxx 90/186 doc id 7516 rev 8 11.3.7 register description status register (scisr) reset value: 1100 0000 (c0h) 7 0 tdre tc rdrf idle or nf fe pe read only 7 tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interr upt is generated if the tie bit=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a write to the scidr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note: data will not be transferred to the shift register unless the tdre bit is cleared. 6tc transmission complete. this bit is set by hardware when transmission of a frame containing data is complete. an interrupt is generated if tcie=1 in the scicr2 register. it is cleared by a software sequence (an access to the sc isr register followed by a write to the scidr register). 0: transmission is not complete 1: transmission is complete note: tc is not set after the transmission of a preamble or a break. 5 rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred to the scidr register. an interr upt is generated if rie=1 in the scicr2 register. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: data is not received 1: received data is ready to be read 4idle idle line detect. this bit is set by hardware when a idle line is detected. an interrupt is generated if the ilie=1 in the scicr2 re gister. it is cleared by a so ftware sequence (an access to the scisr register followed by a read to the scidr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line occurs).
st7263bxx on-chip peripherals doc id 7516 rev 8 91/186 3 or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the scicr2 regist er. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register conten t will not be lost but the shift register will be overwritten. 2nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it appears at the same time as the rdrf bit which itself generates an interrupt. 1 fe framing error. this bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. it is cleared by a software sequence (an access to the scisr register followed by a read to the scidr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it appears at the same time as the rdrf bit which itself generates an inte rrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. 0 pe parity error. this bit is set by hardware when a parity e rror occurs in receiver mode. it is cleared by a software sequence (a read to the stat us register followed by an access to the scidr data register). an interrupt is gen erated if pie=1 in the scicr1 register. 0: no parity error 1: parity error
on-chip peripherals st7263bxx 92/186 doc id 7516 rev 8 control register 1 (scicr1) reset value: x000 0000 (x0h) 7 0 r8 t8 scid m wake pce ps pie read/write 7 r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. 6 t8 transmit data bit 8. this bit is used to store the 9th bi t of the transmitted word when m=1. 5 scid disabled for low power consumption when this bit is set the sci prescalers an d outputs are stopped and the end of the current byte transfer in order to reduce power consumption.this bit is set and cleared by software. 0: sci enabled 1: sci prescaler and outputs disabled 4 m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit note: the m bit must not be modified during a data transfer (both transmission and reception). 3 wake wakeup method. this bit determines the sci wakeup method, it is set or cleared by software. 0: idle line 1: address mark 2 pce parity control enable. this bit selects the hardware parity co ntrol (generation and detection). when the parity control is enabled, the computed parity is inserted at the msb position (9th bit if m=1; 8th bit if m=0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmission). 0: parity control disabled 1: parity control enabled 1 ps parity selection. this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected after the current byte. 0: even parity 1: odd parity 0 pie parity interrupt enable. this bit enables the interrupt capability of the hardware parity control when a parity error is detected (pe bit set). it is set and cleared by software. 0: parity error interrupt disabled 1: parity error interrupt enabled.
st7263bxx on-chip peripherals doc id 7516 rev 8 93/186 control register 2 (scicr2) reset value: 0000 0000 (00h) 7 0 tie tcie rie ilie te re rwu sbk read/write 7tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated wh enever tdre=1 in the scisr register 6tcie transmission complete interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the scisr register 5 rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the scisr register 4ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the scisr register. 3te transmitter enable. this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note: during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word. when te is set there is a 1 bit-time delay before the transmission starts. caution: the tdo pin is free for general purpose i/o only when the te and re bits are both cleared (or if te is never set).
on-chip peripherals st7263bxx 94/186 doc id 7516 rev 8 data register (scidr) reset value: undefined this register contains the received or transmitted data character, depending on whether it is read from or written to. the data register performs a double function (r ead and write) since it is composed of two registers, one for transmission (t dr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift register (see figure 41 ). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 41 ). 2re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit 1rwu receiver wakeup. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wakeup sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: before selecting mute mode (setting the rwu bit), the sci must receive some data first, otherwise it cannot function in mute mode with wakeup by idle line detection. 0 sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to ?1? and then to ?0?, the transmitter will send a break word at the end of the current word. 7 0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 read/write
st7263bxx on-chip peripherals doc id 7516 rev 8 95/186 baud rate register (scibrr) reset value: 0000 0000 (00h) . 7 0 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 read/write [7:6] scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges (see ta b l e 2 9 ). [5:3] sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock (see ta b l e 3 0 ). [2:0] scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp[1: 0] bits define the total division applied to the bus clock to yield the receive rate clock (see ta b l e 3 1 ). table 29. prescaling factors pr prescaling factor scp1 scp0 100 301 410 13 1 1 table 30. tr dividing factors tr dividing factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 table 31. rr dividing factor rr dividing factor scr2 scr1 scr0 1 000 2 001 4 010
on-chip peripherals st7263bxx 96/186 doc id 7516 rev 8 8 011 16 100 32 101 64 110 128 1 1 1 table 32. sci register map and reset values address (hex.) register label 76543210 20 scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 0 pe 0 21 scidr reset value dr7 x dr6 x dr5 x dr4 x dr3 x dr2 x dr1 x dr0 x 22 scibrr reset value scp1 0 scp0 0 sct2 x sct1 x sct0 x scr2 x scr1 x scr0 x 23 scicr1 reset value r8 x t8 x scid 0 m x wake x pce 0 ps 0 pie 0 24 scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 table 31. rr dividing factor rr dividing factor scr2 scr1 scr0
st7263bxx on-chip peripherals doc id 7516 rev 8 97/186 11.4 usb interface (usb) 11.4.1 introduction the usb interface implements a low-speed function interface between the usb and the st7 microcontroller. it is a highly integrated circuit which includes the transceiver, 3.3 voltage regulator, sie and dma. no external components are needed apart from the external pull-up on usbdm for low speed recognition by the usb host. the use of dma architecture allows the endpoint definition to be completely flexible. endpoints can be configured by software as in or out. 11.4.2 main features usb specification version 1.1 compliant supports low-speed usb protocol two or three endpoints (including default one) depending on the device (see device feature list and register map) crc generation/checking, nrzi encoding/decoding and bit-stuffing usb suspend/resume operations dma data transfers on-chip 3.3 v regulator on-chip usb transceiver 11.4.3 functional description the block diagram in figure 44 , gives an overview of the usb interface hardware. for general information on the usb, refer to the ?universal serial bus specifications? document available at http//:www.usb.org. serial interface engine the sie (serial interface engine) interfaces with the usb, via the transceiver. the sie processes tokens, handles data transmission/reception, and handshaking as required by the usb standard. it also performs frame formatting, including crc generation and checking. endpoints the endpoint registers indicate if the microcontroller is ready to transmit/receive, and how many bytes need to be transmitted. dma when a token for a valid endpoint is recognized by the usb interface, the related data transfer takes place, using dma. at the end of the transaction, an interrupt is generated. interrupts by reading the interrupt status register, application software can know which usb event has occurred.
on-chip peripherals st7263bxx 98/186 doc id 7516 rev 8 figure 44. usb block diagram 11.4.4 register description dma address register (dmar) reset value: undefined software must write the start address of the dma memory area whose most significant bits are given by da15-da6. the remaining 6 address bits are set by hardware. see the description of the idr register and figure 45 . cpu memory transceiver 3.3 v voltage regulator sie endpoint dma interrupt address, and interrupts usbdm usbdp usbvcc 6 mhz registers registers data buses usbgnd 7 0 da15 da14 da13 da12 da11 da10 da9 da8 read.write [7:0] da[15:8] dma address bits 15-8.
st7263bxx on-chip peripherals doc id 7516 rev 8 99/186 interrupt/dma register (idr) reset value: xxxx 0000 (x0h) figure 45. dma buffers 7 0 da7 da6 ep1 ep0 cnt3 cnt2 cnt1 cnt0 read.write [7:6] da[7:6] dma address bits 7-6. software must reset these bits. see the description of the dmar register and figure 45 . [5:4] ep[1:0] endpoint number (read-only). these bits identify the endpoint which required attention. 00: endpoint 0 01: endpoint 1 10: endpoint 2 when a ctr interrupt occurs (see register istr) the software should read the ep bits to identify the endpoint which has sent or received a packet. [3:0] cnt[3:0] byte count (read only). this field shows how many data bytes have been received during the last data reception. note: not valid for data transmission. endpoint 0 rx endpoint 0 tx endpoint 2 rx endpoint 1 tx 000000 000111 001000 001111 010000 010111 011000 011111 da15-6,000000 endpoint 1 rx endpoint 2 tx 100000 100111 101000 101111
on-chip peripherals st7263bxx 100/186 doc id 7516 rev 8 pid register (pidr) reset value: xx00 0000 (x0h) 7 0 tp3tp2000 rx_ sez rxd 0 read only [7:6] tp[3:2] token pid bits 3 & 2 . usb token pids are encoded in four bits. tp[3:2] correspond to the variable token pid bits 3 & 2. : pid bits 1 & 0 have a fixed value of 01. note: when a ctr interrupt occurs (see register istr) the software should read the tp3 and tp2 bits to retrieve the pid name of the token received. the usb standard defines tp bits (see ta bl e 3 3 ). [5:3] reserved. forced by hardware to 0. 2 rx_sez received single-ended zero this bit indicates the status of the rx_sez transceiver output. 0: no se0 (single-ended zero) state 1: usb lines are in se0 (single-ended zero) state 1 rxd received data 0: no k-state 1: usb lines are in k-state this bit indicates the status of the rxd transceiver output (differential receiver output). if the environment is noisy, the rx_sez and rxd bits can be used to secure the application. by interpreting the status, software can distinguish a valid end suspend event from a spurious wakeup due to noise on the external usb line. a valid end suspend is followed by a resume or reset sequence. a resume is indicated by rxd=1, a reset is indicated by rx_sez=1. 0 reserved. forced by hardware to 0. table 33. tp bit definition tp3 tp2 pid name 00 out 10 in 11 setup
st7263bxx on-chip peripherals doc id 7516 rev 8 101/186 interrupt status register (istr) reset value: 0000 0000 (00h) when an interrupt occurs these bits are set by hardware. software must read them to determine the interrupt type and clear them after servicing. note: these bits cannot be set by software. 7 0 susp dovr ctr err iovr esusp reset sof read.write 7 susp suspend mode request . this bit is set by hardware when a constant idle state is present on the bus line for more than 3 ms, indicating a suspend mode request from the usb bus. the suspend request check is active immediately after each usb reset event and its disabled by hardware when suspend mode is forced (fsusp bit of ctlr register) until the end of resume sequence. 6 dovr dma over/underrun . this bit is set by hardware if the st7 processor can?t answer a dma request in time. 0: no over/underrun detected 1: over/underrun detected 5 ctr correct transfer. this bit is set by hardware when a correct transfer operation is performed. the type of transfer can be determined by looking at bits tp3-tp2 in register pidr. the endpoint on which the tr ansfer was made is identified by bits ep1-ep0 in register idr. 0: no correct transfer detected 1: correct transfer detected note: a transfer where the device sent a nak or stall handshake is considered not correct (the host only sends ack hand shakes). a transfer is considered correct if there are no errors in the pid and crc fields, if the data0/data1 pid is sent as expected, if there were no data overruns, bit stuffing or framing errors. 4 err error. this bit is set by hardware whenever one of the errors listed below has occurred: 0: no error detected 1: timeout, crc, bit stuffing or nonstandard framing error detected 3 iovr interrupt overrun. this bit is set when hardware tries to set err, or sof before they have been cleared by software. 0: no overrun detected 1: overrun detected
on-chip peripherals st7263bxx 102/186 doc id 7516 rev 8 note: to avoid spurious clearing of some bits, it is recommended to clear them using a load instruction where all bits which must not be altered are set, and all bits to be cleared are reset. avoid read-modify-write instructions like and, xor. interrupt mask register (imr) these bits are mask bits for all interrupt condition bits included in the istr. whenever one of the imr bits is set, if the corresponding istr bit is set, and the i bit in the cc register is cleared, an interrupt request is generated. for an explanation of each bit, please refer to the corresponding bit description in istr. reset value: 0000 0000 (00h) 2 esusp end suspend mode . this bit is set by hardware when, during suspend mode, activity is detected that wakes the usb interface up from suspend mode. this interrupt is serviced by a specific vector, in order to wake up the st7 from halt mode. 0: no end suspend detected 1: end suspend detected 1 reset usb reset. this bit is set by hardware when the usb reset sequence is detected on the bus. 0: no usb reset signal detected 1: usb reset signal detected note: the daddr, ep0ra, ep0rb, ep1ra, ep1rb, ep2ra and ep2rb registers are reset by a usb reset. 0 sof start of frame. this bit is set by hardware when a low-speed sof indication (keep-alive strobe) is seen on the usb bus. it is also issued at the end of a resume sequence. 0: no sof signal detected 1: sof signal detected 7 0 suspm dovrm ctrm errm iovrm esuspm resetm sofm read.write
st7263bxx on-chip peripherals doc id 7516 rev 8 103/186 control register (ctlr) reset value: 0000 0110 (06h) device address register (daddr) reset value: 0000 0000 (00h) 7 0 0 0 0 0 resume pdwn fsusp fres read/write [7:4] reserved. forced by hardware to 0. 3 resume resume . this bit is set by software to wakeup the host when the st7 is in suspend mode. 0: resume signal not forced 1: resume signal forced on the usb bus. software should clear this bit after the appropriate delay. 2 pdwn power down . this bit is set by software to turn o ff the 3.3 v on-chip voltage regulator that supplies the external pull-up resistor and the transceiver. 0: voltage regulator on 1: voltage regulator off note: after turning on the voltage regulator, software should allow at least 3 s for stabilization of the power supply before using the usb interface. 1 fsusp force suspend mode . this bit is set by software to enter suspend mode. the st7 should also be halted allowing at least 600 ns before issuing the halt instruction. 0: suspend mode inactive 1: suspend mode active when the hardware detects usb activity, it re sets this bit (it can also be reset by software). 0 fres force reset. this bit is set by software to force a rese t of the usb interface, just as if a reset sequence came from the usb. 0: reset not forced 1: usb interface reset forced. the usb is held in reset st ate until software clears th is bit, at which point a ?usb- reset? interrupt will be generated if enabled. 7 0 0 add6 add5 add4 add3 add2 add1 add0 read.write 7 reserved. forced by hardware to 0. [6:0] add[6:0] device address, 7 bits. software must write into this register the address sent by the host during enumeration. note: this register is also reset when a usb reset is received from the usb bus or forced through bit fres in the ctlr register.
on-chip peripherals st7263bxx 104/186 doc id 7516 rev 8 endpoint n register a (epnra) these registers (ep0ra, ep1r a and ep2ra) are used for c ontrolling data transmission. they are also reset by the usb bus reset. note: endpoint 2 and the ep2ra register are not available on some devices (see device feature list and register map). reset value: 0000 xxxx (0xh) 7 0 st_ out dtog _tx stat _tx1 stat _tx0 tbc3 tbc2 tbc1 tbc0 read.write 7 st_out status out. this bit is set by software to indicate that a status out packet is expected: in this case, all nonzero out data transfers on the endpoint are stalled instead of being acked. when st_out is reset, out transactions can have any number of bytes, as needed. 6 dtog_tx data toggle, for transmission transfers. it contains the required value of the toggle bit (0=data0, 1=data1) for the next transmitted data packet. this bit is set by hardware at the reception of a setup pid. dtog_tx toggles only when the transmitter has received the ack signal from the usb host. dtog_tx and also dt og_rx (see epnrb) are normally updated by hardware, at the receipt of a relevant pid. they can be also written by software. [5:4] stat_tx[1:0] status bits, for transmission transfers. these bits contain the information about the endpoint status, which are listed in ta bl e 3 4 . these bits are written by software. hardwa re sets the stat_tx bits to nak when a correct transfer has occurred (ctr=1) re lated to a in or setup transaction addressed to this endpoint; this allows th e software to prepare the next set of data to be transmitted. [3:0] tbc[3:0] transmit byte count for endpoint n. before transmission, after filling the transm it buffer, software must write in the tbc field the transmit packet size expressed in bytes (in the range 0-8). caution: any value outside the range 0-8 willin duce undesired effects (such as continuous data transmission). table 34. stat_tx bit definition stat_tx1 stat_tx0 meaning 00 disabled: transmission transfers cannot be executed. 01 stall : the endpoint is stalled and all transmission requests result in a stall handshake. 10 nak : the endpoint is naked and all transmission requests result in a nak handshake. 11 valid : this endpoint is enabled for transmission.
st7263bxx on-chip peripherals doc id 7516 rev 8 105/186 endpoint n register b (epnrb) these registers (ep1rb and ep2rb) are used for controlling data reception on endpoints 1 and 2. they are also reset by the usb bus reset. note: endpoint 2 and the ep2rb register are not available on some devices (see device feature list and register map). reset value: 0000 xxxx (0xh) 7 0 ctrl dtog _rx stat _rx1 stat _rx0 ea3 ea2 ea1 ea0 read.write 7 ctrl control. this bit should be 0. note: if this bit is 1, the endpoint is a control endpoint. (endpoint 0 is always a control endpoint, but it is possible to have more than one control endpoint). 6 dtog_rx data toggle, for reception transfers . it contains the expected val ue of the toggle bit (0=data0, 1=data1) for the next data packet. this bit is cleared by hardwa re in the first stage (setup stage) of a control transfer (setup transactions st art always with data0 pid). the receiver toggles dtog_rx only if it receives a correct data packet and the packet?s data pid matches the receiver sequence bit. [5:4] stat_rx [1:0] status bits, for reception transfers. these bits contain the information about the endpoint status, which are listed in ta b l e 3 5 . these bits are written by software. hardware sets the stat_rx bits to nak when a correct transfer has occurred (ctr=1) related to an out or setup transaction addressed to this endpoint, so the software has the time to elaborate the received data before acknowledging a new transaction. [3:0] ea[3:0] endpoint address . software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. usually ep1rb contains ?0001? and ep2rb contains ?0010?. table 35. stat_rx bit definition stat_rx1 stat_rx0 meaning 00 disabled : reception transfers cannot be executed. 01 stall: the endpoint is stalled and all reception requests result in a stall handshake. 10 nak : the endpoint is naked and all reception requests result in a nak handshake. 11 valid : this endpoint is enabled for reception.
on-chip peripherals st7263bxx 106/186 doc id 7516 rev 8 endpoint 0 register b (ep0rb) this register is used for controlling data recept ion on endpoint 0. it is also reset by the usb bus reset. reset value: 1000 0000 (80h) 11.4.5 programming considerations the interaction between the usb interface and the application program is described below. apart from system reset, action is always initia ted by the usb interface, driven by one of the usb events associated with the interrupt status register (istr) bits. initializing the registers at system reset, the software must initialize all registers to enable the usb interface to properly generate interrupts and dma requests. 1. initialize the dmar, idr, and imr registers (choice of enabled interrupts, address of dma buffers). refer the paragraph titled initializing the dma buffers. 2. initialize the ep0ra and ep0rb registers to enable accesses to address 0 and endpoint 0 to support usb enumeration. refer to the paragraph titled endpoint initialization. 3. when addresses are received through this channel, update the content of the daddr. 4. if needed, write the endpoint numbers in the ea fields in the ep1rb and ep2rb register. initializing dma buffers the dma buffers are a contiguous zone of memory whose maximum size is 48 bytes. they can be placed anywhere in the memory space to enable the reception of messages. the 10 most significant bits of the start of this memory area are specified by bits da15-da6 in registers dmar and idr, the remaining bits are 0. the memory map is shown in figure 45 . each buffer is filled starting from the bottom (last 3 address bits=000) up. endpoint initialization to be ready to receive, set stat_rx to valid (11b) in ep0rb to enable reception. to be ready to transmit: 1. write the data in the dma transmit buffer. 2. in register epnra, specify the number of bytes to be transmitted in the tbc field 3. enable the endpoint by setting the stat_tx bits to valid (11b) in epnra. 7 0 1 dtog rx stat rx1 stat rx0 0000 read.write 7 forced by hardware to 1. [6:4] refer to the epnrb register for a description of these bits. [3:0] forced by hardware to 0.
st7263bxx on-chip peripherals doc id 7516 rev 8 107/186 note: once transmission and/or reception are enabled, registers epnra and/or epnrb (respectively) must not be modified by software, as the hardware can change their value on the fly. when the operation is completed, they can be accessed again to enable a new operation. interrupt handling start of frame (sof) the interrupt service routine may monitor the sof events for a 1 ms synchronization event to the usb bus. this interrupt is generated at the end of a resume sequence and can also be used to detect this event. usb reset (reset) when this event occurs, the daddr register is reset, and communicati on is disabled in all endpoint registers (the usb interface will not respond to any packet). software is responsible for reenabling endpoint 0 within 10 ms of the end of reset. to do this, set the stat_rx bits in the ep0rb register to valid. suspend (susp) the cpu is warned about the lack of bus activity for more than 3 ms, which is a suspend request. the software should set the usb interface to suspend mode and execute an st7 halt instruction to meet the usb-specified power constraints. end suspend (esusp) the cpu is alerted by activity on the usb, which causes an esusp interrupt. the st7 automatically terminates halt mode. correct transfer (ctr) 1. when this event occurs, the hardware automatically sets the stat_tx or stat_rx to nak. every valid endpoint is naked until software clears the ctr bit in the istr register, independently of the endpoint number addressed by the transfer which generated the ctr interrupt. if the event triggering the ctr interrupt is a setup transaction, both stat_tx and stat_rx are set to nak. 2. read the pidr to obtain the token and the idr to get the endpoint number related to the last transfer. when a ctr interrupt occurs, the tp3-tp2 bits in the pidr register and ep1-ep0 bits in the idr register stay unchanged until the ctr bit in the istr register is cleared. 3. clear the ctr bit in the istr register. table 36. usb register map and reset values address (hex.) register name 76 5 43210 25 pidr reset value tp3 x tp2 x 0 0 0 0 0 0 rx_sez 0 rxd 0 0 0 26 dmar reset value da15 x da14 x da13 x da12 x da11 x da10 x da9 x da8 x
on-chip peripherals st7263bxx 108/186 doc id 7516 rev 8 27 idr reset value da7 x da6 x ep1 x ep0 x cnt3 0 cnt2 0 cnt1 0 cnt0 0 28 istr reset value susp 0 dovr 0 ctr 0 err 0 iovr 0 esusp 0 reset 0 sof 0 29 imr reset value suspm 0 dovrm 0 ctrm 0 errm 0 iovrm 0 esusp m 0 resetm 0 sofm 0 2a ctlr reset value 0 0 0 0 0 0 0 0 resum e 0 pdwn 1 fsusp 1 fres 0 2b daddr reset value 0 0 add6 0 add5 0 add4 0 add3 0 add2 0 add1 0 add0 0 2c ep0ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2d ep0rb reset value 1 1 dtog_rx 0 stat_rx 1 0 stat_rx 0 0 0 0 0 0 0 0 0 0 2e ep1ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 2f ep1rb reset value ctrl 0 dtog_rx 0 stat_rx 1 0 stat_rx 0 0 ea3 x ea2 x ea1 x ea0 x 30 ep2ra reset value st_out 0 dtog_tx 0 stat_tx1 0 stat_tx0 0 tbc3 x tbc2 x tbc1 x tbc0 x 31 ep2rb reset value ctrl 0 dtog_rx 0 stat_rx 1 0 stat_rx 0 0 ea3 x ea2 x ea1 x ea0 x table 36. usb register map and reset values (continued) address (hex.) register name 76 5 43210
st7263bxx on-chip peripherals doc id 7516 rev 8 109/186 11.5 i2c bus interface 11.5.1 introduction the i2c bus interface serves as an interface between the microcontroller and the serial i2c bus. it provides both multimaster and slave functions, and controls all i2c bus-specific sequencing, protocol, arbitration and timing. it supports fast i2c mode (400 khz). 11.5.2 main features parallel-bus/i2c protocol converter multimaster capability 7-bit addressing transmitter/receiver flag end-of-byte transmission flag transfer problem detection i2c master features clock generation i2c bus busy flag arbitration lost flag end of byte transmission flag transmitter/receiver flag start bit detection flag start and stop generation i2c slave features stop bit detection i2c bus busy flag detection of misplaced start or stop condition programmable i2c address detection transfer problem detection end-of-byte transmission flag transmitter/receiver flag 11.5.3 general description in addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i2c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i2c bus and a fast i2c bus. this selection is made by software.
on-chip peripherals st7263bxx 110/186 doc id 7516 rev 8 mode selection the interface can operate in the four following modes: slave transmitter/receiver master transmitter/receiver by default, it operates in slave mode. the interface automatically switches from slave to master after it generates a start condition and from master to slave in case of arbitration loss or a stop generation, allowing then multi-master capability. communication flow in master mode, it initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated in master mode by software. in slave mode, the interface is capable of recognizing its own address (7-bit), and the general call address. the general call address detection may be enabled or disabled by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condition is the address byte; it is always transmitted in master mode. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. refer to figure 46 . figure 46. i2c bus protocol acknowledge may be enabled and disabled by software. the i2c interface address and/or general call address can be selected by software. the speed of the i2c interface may be selected between standard (up to 100 khz) and fast i2c (up to 400 khz). sda/scl line control transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a programmable clock divider which depends on the i2c bus mode. when the i2c cell is enabled, the sda and scl ports must be configured as floating inputs. in this case, the value of the external pull-up resistor used depends on the application. scl sda 12 8 9 msb ack stop start condition condition vr02119b
st7263bxx on-chip peripherals doc id 7516 rev 8 111/186 when the i2c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 47. i2c interface block diagram 11.5.4 functional description refer to the cr, sr1 and sr2 registers in section 11.5.7 . for the bit definitions. by default the i2c interface operates in slave mode (m/sl bit is cleared) except when it initiates a transmit or receive sequence. slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register; then it is compared with the address of the interface or the general call address (if selected by software). address not matched : the interface ignores it and waits for another start condition. address matched the interface generates in sequence: ? acknowledge pulse if the ack bit is set. ? evf and adsl bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register, holding the scl line low (see figure 48 transfer sequencing ev1). next, software must read the dr register to determine from the least significant bit (data direction bit) if the slave must enter receiver or transmitter mode. slave receiver data register (dr) data shift register comparator own address register (oar) clock control register (ccr) status register 1 (sr1) control register (cr) control logic status register 2 (sr2) interrupt clock control data control scl or scli sda or sdai
on-chip peripherals st7263bxx 112/186 doc id 7516 rev 8 following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 48 transfer sequencing ev2). slave transmitter following the address reception and after the sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 48 transfer sequencing ev3). when the acknowledge pulse is received, the evf and btf bits are set by hardware with an interrupt if the ite bit is set. closing slave communication after the last data byte is transferred a stop condition is generated by the master. the interface detects this condition and sets evf and stopf bits with an interrupt if the ite bit is set. then the interface waits for a read of the sr2 register (see figure 48 transfer sequencing ev4). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set with an interrupt if the ite bit is set. if it is a stop, then the interface discards the data, released the lines and waits for another start condition. if it is a start, then the interface discards the data and waits for the next slave address on the bus. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set with an interrupt if the ite bit is set. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. note: in case of errors, scl line is not held low; however, the sda line can remain low if the last bits transmitted are all 0. while af=1, the sc l line may be held low due to sb or btf flags that are set at the same time. it is then necessary to release both lines by software. how to release the sda / scl lines set and subsequently clear the stop bit while btf is set. the sda/scl lines are released after the transfer of the current byte. master mode to switch from default slave mode to master mode, a start condition generation is needed. start condition
st7263bxx on-chip peripherals doc id 7516 rev 8 113/186 setting the start bit while the busy bit is cleared causes the interface to switch to master mode (m/sl bit set) and generates a start condition. once the start condition is sent, the evf and sb bits are set by hardware with an interrupt if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the dr register with the slave address byte, holding the scl line low (see figure 48 transfer sequencing ev5). slave address transmission then the slave address byte is sent to the sda line via the internal shift register. after completion of this transfer (and acknowledge from the slave if the ack bit is set), the evf bit is set by hardware with interrupt generation if the ite bit is set. then the master waits for a read of the sr1 register followed by a write in the cr register (for example set pe bit), holding the scl line low (see figure 48 transfer sequencing ev6). next the master must enter receiver or transmitter mode. master receiver following the address transmission and after the sr1 and cr registers have been accessed, the master receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: acknowledge pulse if the ack bit is set evf and btf bits are set by hardware with an interrupt if the ite bit is set. then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see figure 48 transfer sequencing ev7). to close the communication: before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. master transmitter following the address transmission and after sr1 register has been read, the master sends bytes from the dr register to the sda line via the internal shift register. the master waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see figure 48 transfer sequencing ev8). when the acknowledge bit is received, the interface sets, evf and btf bits with an interrupt if the ite bit is set. to close the communication: after writing the last byte to the dr register, set the stop bit to generate the stop condition. the interface goes automatically back to slave mode (m/sl bit cleared). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and berr bits are set by hardware with an interrup t if ite is set. note that berr will not be set if an error is detected during the first or second pulse of
on-chip peripherals st7263bxx 114/186 doc id 7516 rev 8 each 9-bit transaction: single master mode if a start or stop is issued during the first or second pulse of a 9-bit transaction, the berr flag will not be set and transfer will co ntinue however the busy flag will be reset. to work around this, slave devices should issue a nack when they receive a misplaced start or stop. the reception of a nack or busy by the master in the middle of communication gives the possib ility to reinitiate transmission. multimaster mode normally the berr bit would be set whenever unauthorized transmission takes place while transfer is already in progress. however, an issue will arise if an external master generates an unauthorized start or stop while the i 2 c master is on the first or second pulse of a 9-bit transaction. it is possible to work around this by polling the busy bit during i 2 c master mode transmission. the resetting of the busy bit can then be handled in a similar manner as the berr flag being set. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. the af bit is cleared by reading the i2csr2 register. however, if read before the completion of the transmission, the af flag will be set again, thus possibly generating a new interrupt. software must ensure either that the scl line is back at 0 before reading the sr2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. arlo: detection of an arbitration lost condition. in this case the arlo bit is set by hardware (with an interrupt if the ite bit is set and the interface goes automatically back to slave mode (the m/sl bit is cleared). note: in all these cases, the scl lin e is not held low; however, the sda line can remain low if the last bits transmitted are all 0. while af=1, the scl line may be held low due to sb or btf flags that are set at the same time. it is then necessary to release both lines by software.
st7263bxx on-chip peripherals doc id 7516 rev 8 115/186 figure 48. transfer sequencing 1. legend: s=start, p=stop, a=acknowledge, na=non-acknowledge evx=event (with interrupt if ite=1) ev1: evf=1, adsl=1, cleared by reading the sr1 register. ev2: evf=1, btf=1, cleared by reading the sr1 register followed by reading the dr register. ev3: evf=1, btf=1, cleared by reading the sr1 register followed by writing the dr register. ev3-1: evf=1, af=1, btf=1; af is cleared by r eading the sr1 register. the btf is cleared by releasing the lines (stop=1, stop=0) or by writing the dr register (dr=ffh). note: if lines are released by stop=1, stop=0, the subsequent ev4 is not seen. ev4: evf=1, stopf=1, cleared by reading the sr2 register. ev5: evf=1, sb=1, cleared by reading the sr1 register followed by writing the dr register. ev6: evf=1, cleared by reading the sr1 register followed by writing the cr register (for example pe=1). ev7: evf=1, btf=1, cleared by reading the sr1 register followed by reading the dr register. ev8: evf=1, btf=1, cleared by reading the sr1 register followed by writing the dr register. table 37. slave receiver s addres s a data1 a data2 a ..... datan a p ev 1 ev 2 ev 2 ev 2 ev 4 table 38. slave transmitter s addres s a data1 a data2 a ..... datan n a p ev 1 ev 3 ev 3 ev 3 ev3 -1 ev 4 table 39. master receiver s addres s a data1 a data2 a ..... datan n a p ev 5 ev 6 ev 7 ev 7 ev 7 table 40. master transmitter s addres s a data1 a data2 a ..... datan a p ev 5 ev 6 ev 8 ev 8 ev 8 ev 8
on-chip peripherals st7263bxx 116/186 doc id 7516 rev 8 11.5.5 low power modes 11.5.6 interrupts figure 49. event flags and interrupt generation 1. evf can also be set by ev6 or an error from the sr2 register. the i2c interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc register is reset (rim instruction). table 41. low power modes mode description wait no effect on i2c interface. i2c interrupts cause the device to exit from wait mode. halt i2c registers are frozen. in halt mode, the i2c interface is inactive and does not acknowledge data on the bus. the i2c interface resumes operation when the mcu is woken up by an interrupt with ?exit from halt mode? capability. table 42. interrupts interrupt event event flag enable control bit exit from wait exit from halt end of byte transfer event btf ite ye s n o address matched event (slave mode) adsl yes no start bit generation event (master mode) sb yes no acknowledge failure event af yes no stop detection event (slave mode) stopf yes no arbitration lost event (multimaster configuration) arlo yes no bus error event berr yes no btf adsl sb af stopf arlo berr evf interrupt ite (1)
st7263bxx on-chip peripherals doc id 7516 rev 8 117/186 11.5.7 register description i2c control register (cr) reset value: 0000 0000 (00h) 7 0 0 0 pe engc start ack stop ite read/write [7:6] reserved. forced to 0 by hardware. 5 pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master/slave capability note: when pe=0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released while pe=0. when pe=1, the corresponding i/o pins are selected by hardware as alternate functions. to enable the i2c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). 4 engc enable general call. this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). the 00h general call address is acknowledged (01h ignored). 0: general call disabled 1: general call enabled note: in accordance with the i 2 c standard, when gcal addressing is enabled, an i 2 c slave can only receive data. it w ill not transmit data to the master. 3 start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interfac e is disabled (pe=0) or when the start condition is sent (with interrupt generation if ite=1). in master mode: 0: no start generation 1: repeated start generation in slave mode: 0: no start generation 1: start generation when the bus is free
on-chip peripherals st7263bxx 118/186 doc id 7516 rev 8 2 ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received 1 stop generation of a stop condition . this bit is set and cleared by software. it is also cleared by hardware in master mode. note: this bit is not cleared when the interface is disabled (pe=0). in master mode: 0: no stop generation 1: stop generation after the current byte tr ansfer or after the current start condition is sent. the stop bit is cleared by hardware when the stop condition is sent. in slave mode: 0: no stop generation 1: release the scl and sda lines after the current byte transfer (btf=1). in this mode the stop bit has to be cleared by software. 0 ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0: interrupts disabled 1: interrupts enabled refer to figure 49 for the relationship between the events and the interrupt. scl is held low when the sb, btf or adsl flags or an ev6 event (see figure 48 ) is detected.
st7263bxx on-chip peripherals doc id 7516 rev 8 119/186 i2c status register 1 (sr1) reset value: 0000 0000 (00h) 7 0 evf 0 tra busy btf adsl m/sl sb read only 7 evf event flag this bit is set by hardware as soon as an event occurs. it is cleared by software reading sr2 register in case of error event or as described in figure 48 . it is also cleared by hardware when the interface is disabled (pe=0). 0: no event 1: one of the following events has occurred: btf=1 (byte received or transmitted) adsl=1 (address matched in slave mode while ack=1) sb=1 (start condition generated in master mode) af=1 (no acknowledge received after byte transmission) stopf=1 (stop condition detected in slave mode) arlo=1 (arbitration lost in master mode) berr=1 (bus error, misplaced start or stop condition detected) address byte successfully transmitted in master mode. 6 reserved. forced to 0 by hardware. 5 tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after detection of stop condition (stopf=1), loss of bus ar bitration (arlo=1) or when the interface is disabled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted 4 busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. the busy flag of the i2csr1 register is cleared if a bus error occurs. 0: no communication on the bus 1: communication ongoing on the bus note: the busy flag is not updated when the interface is disabled (pe=0). this can have consequences when operating in multimaster mode; i.e. a second active i 2 c master commencing a transfer with an unset busy bit can cause a conflict resulting in lost data. a so ftware workaround consists of checking that the i 2 c is not busy before enabling the i 2 c multimaster cell.
on-chip peripherals st7263bxx 120/186 doc id 7516 rev 8 3 btf byte transfer finished. this bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr register. it is also cleared by hardware when the interface is disabled (pe=0). following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is se nt, this bit is set only after the ev6 event (see figure 48 ). btf is cleared by reading sr1 register followed by writing the next byte in dr register. following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded 2 adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address matched with the oar register content or a general call is recognized. an interrupt is generated if it e=1. it is cleared by software reading sr1 register or by hardware when the interface is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched 1 m/sl master/slave. this bit is set by hardware as soon as the interface is in master mode (writing start=1). it is cleared by hardware after detecting a stop condition on the bus or a loss of arbitration (arlo=1). it is also cleared when the interface is disabled (pe=0). 0: slave mode 1: master mode 0 sb start bit (master mode). this bit is set by hardware as soon as the start condition is generated (following a write start=1). an interrupt is generated if ite=1. it is cleared by software reading sr1 register followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disabled (pe=0). 0: no start condition 1: start condition generated
st7263bxx on-chip peripherals doc id 7516 rev 8 121/186 i2c status register 2 (sr2) reset value: 0000 0000 (00h) 7 0 0 0 0 af stopf arlo berr gcal read only [7:5] reserved. forced to 0 by hardware. 4 af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). 0: no acknowledge failure 1: acknowledge failure note: while af=1, the scl line may be held low due to sb or btf flags that are set at the same time. it is then necessary to release both lines by software. 3 stopf stop detection (slave mode). this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected
on-chip peripherals st7263bxx 122/186 doc id 7516 rev 8 i2c clock control register (ccr) reset value: 0000 0000 (00h) 2 arlo arbitration lost . this bit is set by hardware when the interface loses the arbitration of the bus to another master. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). after an arlo event the interface switch es back automatically to slave mode (m/sl=0). the scl line is not held low while arlo=1. 0: no arbitration lost detected 1: arbitration lost detected note: in a multimaster environment, when the interface is configured in master receive mode it does not perform arbitration during the reception of the acknowledge bit. mishandling of the ar lo bit from the i2csr2 register may occur when a second master simultaneously requests the same data from the same slave and the i 2 c master does not acknowledge the data. the arlo bit is then left at 0 instead of being set. 1 berr bus error. this bit is set by hardware when the interface detects a misplaced start or stop condition. an interrupt is generated if it e=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition note: if a bus error occurs, a stop or a repeated start condition should be generated by the master to re-syn chronize communication, get the transmission acknowledged and the bus released for further communication 0 gcal general call (slave mode). this bit is set by hardware when a general call address is detected on the bus while engc=1. it is cleared by hardware detecting a stop condition (stopf=1) or when the interface is disabled (pe=0). 0: no general call address detected on bus 1: general call address detected on bus 7 0 fm/sm cc6 cc5 cc4 cc3 cc2 cc1 cc0 read/write 7 fm/sm fast/standard i2c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe=0). 0: standard i2c mode 1: fast i2c mode [6:0] cc[6:0] 7-bit clock divider. these bits select the speed of the bus (f scl ) depending on the i2c mode. they are not cleared when the interface is disabled (pe=0). refer to the electrical characteristics section for the table of value. note: the programmed f scl assumes no load on scl and sda lines.
st7263bxx on-chip peripherals doc id 7516 rev 8 123/186 i2c data register (dr) these bits contain the byte to be received or transmitted on the bus. transmitter mode: byte transmission start automatically when the software writes in the dr register. receiver mode: the first data byte is received automatically in the dr register using the least significant bit of the address. the following data bytes are then received one by one after reading the dr register. reset value: 0000 0000 (00h) i2c own address register (oar) reset value: 0000 0000 (00h) 7 0 d7 d6 d5 d4 d3 d2 d1 d0 read/write 7 0 add7 add6 add5 add4 add3 add2 add1 add0 read/write [7:1] add[7:1] interface address . these bits define the i2c bus address of the interface. they are not cleared when the interface is disabled (pe=0). 0 add0 address direction bit. this bit is don?t care, the interface acknowledges either 0 or 1. it is not cleared when the interface is disabled (pe=0). note: address 01h is always ignored.
on-chip peripherals st7263bxx 124/186 doc id 7516 rev 8 note: refer to section 16: known limitations for information regarding a limitation on the alternate function on pin pa2 (scl). table 43. i2c register map address (hex.) register name 765 4 3210 39 dr dr7 .. dr0 3b oar add7 .. add0 3c ccr fm/sm cc6 .. cc0 3d sr2 af stopf arlo berr gcal 3e sr1 evf tra busy btf adsl m/sl sb 3f cr pe engc start ack stop ite
st7263bxx on-chip peripherals doc id 7516 rev 8 125/186 11.6 8-bit a/d converter (adc) 11.6.1 introduction the on-chip analog to digital converter (adc) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 11.6.2 main features 8-bit conversion up to 12 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 50 . 11.6.3 functional description analog power supply v dda and v ssa are the high and low level reference voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. see electrical characteristics section for more details.
on-chip peripherals st7263bxx 126/186 doc id 7516 rev 8 figure 50. adc block diagram digital a/d conversion result the conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the conversion result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the parametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and samp ling not being completed in the allotted time. a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 51 : sample capacitor lo ading [duration: t load ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. a/d conversion [duration: t conv ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. while the adc is on, these two phases are continuously repeated. at the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. the advantage of this behavior is that it minimizes the current consumption on the analog pin in case of single input channel measurement. ch2 ch1 ch3 coco 0 adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c adc d2 d1 d3 d7 d6 d5 d4 d0 adcdr 4 div 4 f adc f cpu hold control
st7263bxx on-chip peripherals doc id 7516 rev 8 127/186 software procedure refer to the control/status register (csr) and data register (dr) in section 11.6.6 for the bit definitions and to figure 51 for the timings. adc configuration the total duration of the a/d conversion is 12 adc clock periods (1/f adc =4/f cpu ). the analog input ports must be configured as input, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: select the ch[3:0] bits to assign the analog channel to be converted. adc conversion in the csr register: set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: the coco bit is set by hardware. no interrupt is generated. the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the coco bit and starts a new conversion. figure 51. adc conversion timings 11.6.4 low power modes note: the a/d converter may be disabled by resetting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. adccsr write adon coco bit set t load t conv operation hold control table 44. low power modes mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilization time before accurate conversions can be performed.
on-chip peripherals st7263bxx 128/186 doc id 7516 rev 8 11.6.5 interrupts none 11.6.6 register description control/status register (csr) reset value: 0000 0000 (00h) 7 0 coco 0 adon 0 ch3 ch2 ch1 ch0 read/write 7 coco conversion complete this bit is set by hardware. it is cleared by software reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register 6 reserved. must always be cleared. 5 adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on 4 reserved. must always be cleared. [3:0] ch[3:0] channel selection these bits are set and cleared by software . they select the analog input to convert (see ta bl e 4 5 ). table 45. channel selection channel pin (1) 1. the number of pins and the channel selection varies according to the device. refer to the device pinout. ch3 (2) ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1
st7263bxx on-chip peripherals doc id 7516 rev 8 129/186 data register (dr) this register contains the converted analog value in the range 00h to ffh. reset value: 0000 0000 (00h) note: reading this register reset the coco flag. 2. for sdip/so34 devices, the ch3 bit is always at ?0?. if, however, set to ?1? on error, channel (11:8) becomes enabled which may result in a hi gher and unnecessary level of consumption. 7 0 d7 d6 d5 d4 d3 d2 d1 d0 read only table 46. adc register map address (hex.) register name 765 4 3210 0ah dr ad7 .. ad0 0bh csr coco 0 adon 0 ch3 ch2 ch1 ch0
instruction set st7263bxx 130/186 doc id 7516 rev 8 12 instruction set 12.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdivided in two sub-modes called long and short: long addressing mode is more powerful because it can use the full 64 kbyte address space, however it uses more bytes and more cpu cycles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory instructions use shor t addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 47. addressing modes addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 table 48. st7 addressing mode overview mode syntax destination/ source pointer address pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2
st7263bxx instruction set doc id 7516 rev 8 131/186 12.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required information for the cpu to process the operation. long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc- 128/pc+127 (1) + 1 relative indirect jrne [$10] pc- 128/pc+127 (1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3 1. at the time the instruction is executed, the program counter (pc) points to the instruction following jrxx. table 48. st7 addressing mode overview (continued) mode syntax destination/ source pointer address pointer size (hex.) length (bytes) table 49. inherent instructions inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero
instruction set st7263bxx 132/186 doc id 7516 rev 8 12.1.2 immediate instructions immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. 12.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub-modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte addressing space, but requires 2 bytes after the opcode. 12.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc sh ift and rotate operations swap swap nibbles table 49. inherent instructions (continued) inherent instruction function table 50. immediate instructions immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st7263bxx instruction set doc id 7516 rev 8 133/186 indexed (short) the offset is a byte, thus requires only one byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte addressing space and requires 2 bytes after the opcode. 12.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (pointer). the pointer address follows the opcode. the indirect addressing mode consists of two sub- modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. 12.1.6 indirect i ndexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (x or y) with a pointer value located in memory. the pointer address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 51. instructions supporting direct, in dexed, indirect and indirect indexed addressing modes long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtraction operations
instruction set st7263bxx 134/186 doc id 7516 rev 8 12.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub-modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the address follows the opcode. bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump operations sll, srl, sra, rlc, rrc sh ift and rotate operations swap swap nibbles call, jp call or jump subroutine table 51. instructions supporting direct, in dexed, indirect and indirect indexed addressing modes (continued) long and short instructions function table 52. instructions supporting relative addressing mode available relative direct/ind irect instructions function jrxx conditional jump callr call relative
st7263bxx instruction set doc id 7516 rev 8 135/186 12.2 instruction groups the st7 family devices use an instruction set co nsisting of 63 instruct ions. the instructions may be subdivided into 13 main groups as illustra ted in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available opcodes for an 8-bit cpu (256 opcodes), three different prebyte opcodes are defined. these prebytes modify the meaning of the instruction they precede. the whole instruction becomes: pc-2end of previous instruction pc-1prebyte pcopcode pc+1additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruction using indirect x indexed addressing mode. piy 91replace an instruction using x indirect indexed addressing mode by a y one. table 53. instruction groups load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf
instruction set st7263bxx 136/186 doc id 7516 rev 8 table 54. instructions mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >=
st7263bxx instruction set doc id 7516 rev 8 137/186 jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/ w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z table 54. instructions (continued) mnemo description function/example dst src h i n z c
electrical characteristics st7263bxx 138/186 doc id 7516 rev 8 13 electrical characteristics 13.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 13.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25 c and t a =t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 13.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd =5 v. they are given only as design guidelines and are not tested. 13.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 13.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 52 . figure 52. pin loading conditions 13.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 53 . c l st7 pin
st7263bxx electrical characteristics doc id 7516 rev 8 139/186 figure 53. pin input voltage 13.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7 k for reset , 10 k for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. v in st7 pin table 55. voltage characteristics symbol ratings maximum value unit v dd - v ss supply voltage 6.0 v v in (1)(2) 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operati on, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7 k for reset, 10 k for i/os). unused i/o pins must be tied in the same way to vdd or vss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical characteristics st7263bxx 140/186 doc id 7516 rev 8 table 56. current characteristics symbol ratings maximum value unit i vdd total current into v dd power lines (source) (1) 80 ma i vss total current out of v ss ground lines (sink) (1) 80 i io output current sunk by any standard i/o and control pin 25 output current sunk by any high sink i/o pin 50 output current source by any i/os and control pin - 25 i inj(pin) (2)(3) injected current on v pp pin 5 injected current on reset pin 5 injected current on oscin and oscout pins 5 injected current on any other pin (4)(5) 5 i inj(pin) (2) total injected current (sum of all i/o and control pins) (4) 20 i inj(pin) (2)(3) negative injected current to pb0 (10 ma)/ain0 pin - 80 a 1. all power (v dd ) and ground (v ss ) lines must be connected to the external supply. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7263bxx electrical characteristics doc id 7516 rev 8 141/186 13.3 operating conditions figure 54. f cpu maximum operating frequency versus v dd supply voltage 13.3.1 operating conditions with low voltage detector (lvd) subject to general operating conditions for v dd , f cpu , and t a . refer to figure 12 on page 33 . table 58. general operating conditions symbol parameter conditions min typ max unit v dd operating supply voltage f cpu = 8 mhz 455.5 v v dda analog reference voltage v dd -v dd v ssa analog reference voltage v ss -v ss f cpu operating frequency f osc = 24 mhz - - 8 mhz f osc = 12 mhz - - 4 t a ambient temperature range 0 - 70 c f cpu [mhz] supply voltage [v] 8 4 2 0 2.5 3.0 3.5 4 4.5 5 5.5 functionality functionality guaranteed from 4 to 5.5 v not guaranteed in this area table 59. operating conditions with lvd symbol parameter conditions min typ max unit v it+ low voltage reset threshold (v dd rising) v dd max. variation 50 v/ms 3.4 3.7 4.0 v v it- low voltage reset threshold (v dd falling) v dd max. variation 50v/ms 3.2 3.5 3.8 v v hyst hysteresis (v it+ - v it- ) (1) 1. guaranteed by characteriza tion - not tested in production. 100 175 220 mv vt por v dd rise time rate (2) 2. the v dd rise time rate condition is needed to insure a correct device power-on and lvd reset. not tested in production. 0.5 - 50 v/ms
electrical characteristics st7263bxx 142/186 doc id 7516 rev 8 13.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over temperature range does not take into account the clock source current consumption. to get the total device consumption, the two current values must be added (except for halt mode for which the clock is stopped). figure 55. typ. i dd in run at f cpu = 4 and 8 mhz table 60. supply current characteristics symbol parameter conditions typ max unit i dd( ta ) supply current variation vs. temperature constant v dd and f cpu -10 (1) % i dd cpu run mode i/os in input mode f cpu = 4 mhz 7.5 9 (2)(1) ma f cpu = 8 mhz 10.5 13 (2) cpu wait mode f cpu = 4 mhz 6 8 (1) ma f cpu = 8 mhz 8.5 11 (2) cpu halt mode (3) lvd disabled 25 40 (1) a usb suspend mode (4) lvd disabled 100 120 a lvd enabled 230 - 1. not tested in production, guar anteed by characterization. 2. oscillator and watchdog running. all others peripherals disabled. 3. usb transceiver and adc are powered down. 4. cpu in halt mode. current consumption of external pull-up (1.5kohms to usbvcc) and pull-down (15kohms to v ssa ) not included. idd run (ma) at fcpu=4 and 8 mhz 0 2 4 6 8 10 12 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) idd run (ma) 8mhz 4mhz a i1559 3
st7263bxx electrical characteristics doc id 7516 rev 8 143/186 figure 56. typ. i dd in wait at f cpu = 4 and 8 mhz 13.5 clock and timing characteristics subject to general operating conditions for v dd , f cpu , and t a . idd wfi (ma) at fcpu=4 and 8 mhz 0 2 4 6 8 10 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) idd wfi (ma) 8mhz 4mhz a i15594 table 61. general timings symbol parameter conditions min typ (1) 1. data based on typical application software. max unit t c(inst) instruction cycle time f cpu =8 mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time (2) t v(it) = t c(inst) + 10 t cpu 2. time measured between interrupt event and interrupt vector fetch. t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. f cpu =8 mhz 10 - 22 t cpu 1.25 - 2.75 s table 62. control timing characteristics symbol parameter conditions value unit min typ. max f osc oscillator frequency - - 24 mhz f cpu operating frequency - - 8 mhz t rl external reset input pulse width 2520 - - ns t porl internal power reset duration 4096 - - t cpu t wdgl watchdog or low voltage reset output pulse width 200 300 - ns
electrical characteristics st7263bxx 144/186 doc id 7516 rev 8 figure 57. typical application with an external clock source t wdg watchdog timeout f cpu = 8mhz 49152 - 3145728 t cpu 6.144 - 393.216 ms t oxov crystal oscillator startup time 20 (1) 30 40 (1) ms t ddr power up rise time from v dd = 0 to 4 v - - 100 (1) ms 1. not tested in production, guar anteed by characterization. table 62. control timing characteristics table 63. external clock source symbol parameter conditions min typ max unit v oscinh oscin input pin high level voltage see figure 57 0.7xv dd -v dd v v oscinl oscin input pin low level voltage v ss -0.3xv dd t w(oscinh) t w(oscinl) oscin high or low time (1) 15 - - ns t r(oscin) t f(oscin) oscin rise or fall time (1) --15 i l oscx input leakage current v ss v in v dd --1 a 1. data based on design simulation and/or technol ogy characteristics, not tested in production. oscin oscout f osc external st72xxx clock source not connected internally v oscinl v oscinh t r(oscin) t f(oscin) t w(oscinh) t w(oscinl) i l 90% 10%
st7263bxx electrical characteristics doc id 7516 rev 8 145/186 figure 58. typical application with a crystal resonator 13.6 memory characteristics subject to general operating conditions for f cpu , and t a unless otherwise specified. 13.6.1 flash memory operating conditions: f cpu = 8 mhz. oscout oscin f osc c l1 c l2 i 2 r f st72xxx resonator table 64. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. guaranteed by design. not tested in production. halt mode (or reset) 2.0 - - v table 65. dual voltage flash memory (1) 1. refer to the flash programming reference manual for the typical hdflash programming and erase timing values. symbol parameter conditions min typ max unit f cpu operating frequency read mode - - 8 mhz write / erase mode, t a =25 c --8 v pp programming voltage 4.0 v v dd 5.5 v 11.4 - 12.6 v i pp v pp current write / erase - 30 - ma t vpp internal v pp stabilization time - 10 - s t ret data retention t a 5 5c 40 - - years n rw write/erase cycles t a =25 c 100 - - cycles
electrical characteristics st7263bxx 146/186 doc id 7516 rev 8 figure 59. two typical applications with v pp pin 1. when the icp mode is not required by the application, v pp pin must be tied to v ss . v pp st72xxx 10k programming tool v pp st72xxx
st7263bxx electrical characteristics doc id 7516 rev 8 147/186 13.7 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. 13.7.1 functional ems (elect romagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forc ing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 66. emc characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz, sdip32 conforms to iec 1000-4-2 4b v fftb fast transient voltage burst limits to be applied through 100 pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz, sdip32 conforms to iec 1000-4-4 4a
electrical characteristics st7263bxx 148/186 doc id 7516 rev 8 13.7.2 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the board and the loading of each pin. 13.7.3 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. static latchup (lu) 3 complementary static tests are required on 10 parts to assess the latchup performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 67. emi characteristics symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit 16/8 mhz s emi peak level (1) 1. data based on characterization results, not tested in production. v dd = 5v, t a = +25 c, sdip32 package conforming to sae j 1752/3 (2) 2. refer to application note an1709 for data on other package types. 0.1 mhz to 30 mhz 36 dbv 30 mhz to 130 mhz 39 130 mhz to 1ghz 26 sae emi level 3.5 - table 68. absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v
st7263bxx electrical characteristics doc id 7516 rev 8 149/186 13.8 i/o port pin characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. figure 60. two typical applications with unused i/o pin table 69. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latchup class t a = +25 c a table 70. general characteristics symbol parameter conditions min typ max unit v il input low level voltage - - 0.3xv dd v v ih input high level voltage 0.7xv dd -- v in input voltage true open drain i/o pins v ss -6.0 v other i/o pins - v dd v hys schmitt trigger voltage hysteresis - 400 - mv i l input leakage current v ss v in v dd --1 a i s static current co nsumption induced by each floating input pin (1) floating input mode - 400 - r pu weak pull-up equivalent resistor (2) v in = v ss v dd =5 v 50 90 120 k c io i/o pin capacitance - 5 - pf t f(io)out output high to low level fall time c l =50pf between 10% and 90% -25- ns t r(io)out output low to high level rise time - 25 - t w(it)in external interrupt pulse time (3) 1--t cpu 1. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 60 ). static peak current value taken at a fixed v in value, based on design simulation and technology characteristics, not tested in pr oduction. this value depends on v dd and temperature values. 2. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics described in figure 61 ). 3. to generate an external interrupt, a mini mum pulse width has to be applied on an i/o port pin configured as an external interrupt source. 10k unused i/o port st72xxx 10k unused i/o port st72xxx v dd
electrical characteristics st7263bxx 150/186 doc id 7516 rev 8 figure 61. typ. i pu vs. v dd figure 62. typ. r pu vs. v dd pull-up current (a) 0 10 20 30 40 50 60 70 80 90 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) pull-up current (a) a i15595 rpu (kohm) 0 20 40 60 80 100 120 140 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) rpu (kohm) a i15596
st7263bxx electrical characteristics doc id 7516 rev 8 151/186 figure 63. v ol standard v dd =5 v table 71. output driving current symbol parameter conditions min max unit v ol (1) output low level voltage for a standard i/o pin when up to 8 pins are sunk at the same time, port a0, port a(3:7), port c(0:2), port d(0:7) v dd =5 v i io =+1.6 ma - 0.4 v output low level voltage for a high sink i/o pin when up to 4 pins are sunk at the same time, port b(0:7) i io =+10 ma - 1.3 output low level voltage for a very high sink i/o pin when up to 2 pins are sunk at the same time, port a1, port a2 i io =+25 ma - 1.5 v oh (2) output high level voltage for an i/o pin when up to 8 pins are sourced at same time i io =-10 ma v dd -1.3 (3) - i io =-1.6 ma v dd -0.8 - 1. the i io current sunk must always respect the absolute maximum rating specified in section 13.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 13.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . 3. the minimum v oh value (with i io =-10ma) depends on the chosen devic e type. for flash devices, min = v dd - 1.3 v and for rom devices, min = v dd - 1.7 v vol_2ma (mv) at vdd=5v 0 50 100 150 200 250 11.522.533.54 iio (ma) vol_2ma (mv) a i15597
electrical characteristics st7263bxx 152/186 doc id 7516 rev 8 figure 64. v ol high sink v dd =5 v figure 65. v ol very high sink v dd =5 v vol_10ma (v) at vdd=5v 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 5 7 9 1113151719 iio (ma) vol_10ma (v) a i1559 8 vol_25ma (v) at vdd=5v 0.35 0.45 0.55 0.65 0.75 0.85 0.95 15 20 25 30 35 iio (ma) vol_25ma (v) a i15599
st7263bxx electrical characteristics doc id 7516 rev 8 153/186 figure 66. v ol standard vs. v dd figure 67. v ol high sink vs. v dd vol_2ma (mv) at iio=2ma 105 110 115 120 125 130 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) vol_2ma (mv) a i17200 vol_10ma (v) at iio=10ma 0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) vol_10ma (v) a i17201
electrical characteristics st7263bxx 154/186 doc id 7516 rev 8 figure 68. v ol very high sink vs. v dd figure 69. |v dd -v oh | @ v dd =5 v (low current) vol_25ma (v) at iio=25ma 0.6 0.65 0.7 0.75 0.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) vol_25ma (v) a i17202 |vdd - voh| (v) at vdd=5v 0 0.05 0.1 0.15 0.2 0.25 0.3 11.522.533.54 -iio (ma) |vdd - voh| (v) a i1720 3
st7263bxx electrical characteristics doc id 7516 rev 8 155/186 figure 70. |v dd -v oh | @ v dd =5 v (high current) figure 71. |v dd -v oh | @ i io =2 ma (low current) |vdd - voh| (v) at vdd=5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2 7 12 17 -iio (ma) |vdd - voh| (v) a i17704 |vdd - voh| (v) at iio=-2ma 0.12 0.125 0.13 0.135 0.14 0.145 0.15 0.155 0.16 0.165 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) |vdd - voh| (v) a i17705
electrical characteristics st7263bxx 156/186 doc id 7516 rev 8 figure 72. |v dd -v oh | @ i io =10 ma (high current) 13.9 control pin characteristics subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. |vdd - voh| (v) at iio=-10ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 4 4.2 4.4 4.6 4.8 5 5.2 5.4 vdd (v) |vdd - voh| (v) a i17706 table 72. asynchronous reset pin symbol parameter conditions min typ max unit v ih input high level voltage 0.7xv dd -v dd v v il input low voltage v ss - 0.3xv d d v v hys schmitt trigger voltage hysteresis (1) - 400 - mv v ol output low level voltage (2) v dd =5 v i io =5 ma - - 0.8 v i io =7.5 ma - - 1.3 r on weak pull-up equivalent resistor (3) v in = v ss v dd =5 v 50 80 100 k t w(rstl)out generated reset pulse duration external pin or internal reset sources - 6 30 - 1/f sfosc s t h(rstl)in external reset pulse hold time (4) 5-- s 1. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 2. the i io current sunk must always respect the absolute maximum rating specified in section 13.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resistive transistor. this data is based on characterization results, not tested in production. 4. to guarantee the reset of the device, a minimum pulse has to be applied to reset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored.
st7263bxx electrical characteristics doc id 7516 rev 8 157/186 figure 73 and figure 74 show the reset circuit which prot ects the device against parasitic resets: the output of the external reset circuit must have an open-drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). whatever the reset source is (internal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section table 72.: asynchronous reset pin . otherwise the reset will not be taken into account internally. because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must ensure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section table 56.: current characteristics . when the lvd is enabled: it is recommended not to connect a pull-up resistor or capacitor. a 10 nf pull-down capacitor is required to filter noise on the reset line. in case a capacitive power supply is used, it is recommended to connect a 1 m pull- down resistor to the reset pin to discharge any residual voltage induced by the capacitive effect of the power supply (thi s will add 5 a to the power consumption of the mcu). tips when using the lvd: a) check that all recommendations related to iccclk and reset circuit have been applied (see notes above). b) check that the power supply is properly decoupled (100 nf + 10 f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100 nf + 1 m pull-down on the reset pin. c) the capacitors connected on the reset pin and also the power supply are key to avoid any start-up marginality. in most cases, steps a) and b) above are sufficient for a robust solution. otherwise: replace 10 nf pull-down on the reset pin with a 5 f to 20 f capacitor. figure 73. reset pin protection when lvd is enabled 0.01 f st72xxx pulse generator filter r on v dd watchdog lvd reset internal reset reset external required 1m optional
electrical characteristics st7263bxx 158/186 doc id 7516 rev 8 figure 74. reset pin protection when lvd is disabled 13.10 communication interface characteristics 13.10.1 usb interface operating conditions t a = 0 to +70 c, v dd = 4.0 to 5.25 v unless otherwise specified. figure 75. usb data signal rise and fall time 0.01 f external reset circuit user required st72xxx pulse generator filter r on v dd watchdog internal reset table 73. usb dc characteristics symbol parameter conditions min. max. unit v di differential input sensitivity i(d+, d-) 0.2 - v (1) v cm differential common mode range includes v di range 0.8 2.5 v se single ended receiver threshold 0.8 2.0 v ol static output low r l (2) of 1.5 k to 3.6 v - 0.3 v oh static output high r l (2) of 15 k to v ss 2.8 3.6 usbv usbvcc: voltage level (3) v dd =5 v 3.00 3.60 1. all the voltages are measured from the local ground potential. 2. r l is the load connected on the usb drivers. 3. to improve emc performance (noise immunity), it is recommended to connect a 100nf capacitor to the usbvcc pin. differential data lines v ss tf tr crossover points vcrs
st7263bxx electrical characteristics doc id 7516 rev 8 159/186 13.10.2 sci interface subject to general operating condition for v dd , f cpu , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (rdi and tdo). table 74. usb low-speed electrical characteristics symbol parameter conditions min max unit driver characteristics: - - t r rise time c l =50 pf (1) 1. for more detailed information, please refer to chapter 7 (electrical) of the usb specification (version 1.1). 75 - ns c l =600 pf (1) -300ns t f fall time c l =50 pf (1) 75 - ns c l =600 pf (1) -300ns t rfm rise/ fall time matching t r /t f 80 120 % v crs output signal crossover voltage 1.3 2.0 v table 75. sci characteristics symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=128, pr=13 tr (or rr)= 32, pr=13 tr (or rr)= 16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 16, pr= 3 tr (or rr)= 2, pr=13 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 38400 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 ~38461.54 hz
electrical characteristics st7263bxx 160/186 doc id 7516 rev 8 13.10.3 i 2 c interface refer to i/o port characteristics for more details on the input/output alternate function characteristics (sdai and scli). the st7 i 2 c interface meets the requirements of the standard i 2 c communication protocol described in the following table. subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. table 76. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. data based on standard i 2 c protocol requirement, not tested in production. fast mode i 2 c (1) (2) 2. at 4 mhz f cpu , max.i 2 c speed (400 khz) is not achiev able. in this case, max. i 2 c speed will be approximately 260 khz. unit min max min max t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. -0 (4) 4. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 20+0.1c b 300 t f(sda) t f(scl) sda and scl fall time - 300 20+0.1c b 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:s ta ) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf
st7263bxx electrical characteristics doc id 7516 rev 8 161/186 figure 76. typical application with i 2 c bus and timing diagram 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd. repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(sck) t r(sck) t w(sckl) t w(sckh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda sck 4.7k sdai st72xxx scli v dd 100 100 v dd 4.7k i 2 cbus
electrical characteristics st7263bxx 162/186 doc id 7516 rev 8 ta bl e 7 7 gives the values to be written in the i2cccr register to obtain the required i 2 c scl line frequency. 13.11 8-bit adc subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. table 77. scl frequency (1)(2)(3)(4) f scl (khz) i2cccr value f cpu =4 mhz f cpu =8 mhz v dd = 4.1 v v dd = 5 v v dd = 4.1 v v dd = 5 v r p =3.3 k r p =4.7 k r p =3.3 k r p =4.7 k r p =3.3 k r p =4.7 k r p =3.3 k r p =4.7 k 400 na na na na 83h 83 83h 83h 300 na na na na 85h 85h 85h 85h 200 83h 83h 83h 83h 8ah 89h 8ah 8ah 100 10h 10h 10h 10h 24h 23h 24h 23h 50 24h 24h 24h 24h 4ch 4ch 4ch 4ch 20 5fh 5fh 5fh 5fh ffh ffh ffh ffh 1. legend: r p = external pull-up resistance; f scl = i 2 c speed; na = not achievable. 2. the above variations depend on the accuracy of the external components used. 3. for speeds around 200 khz, achieved speed can have 5% tolerance. 4. for other speed ranges, achieved speed can have 2% tolerance. table 78. 8-bit adc characteristics symbol parameter conditions min typ (1) 1. unless otherwise specified, typical data are based on t a =25c and v dd -v ss =5v. max unit f adc adc clock frequency - - 4 mhz v ain conversion range voltage (2) 2. when v dda and v ssa pins are not available on the pinout, the adc refer to v dd and v ss. v ssa -v dda v r ain external input resistor - - 10 (3) 3. any added external serial resistor will downgrade the adc accuracy (espec ially for resistance greater than 10k ). data based on characterization results, not tested in production. ? c adc internal sample and hold capacitor -6 -pf t stab stabilization time after adc enable f cpu =8 mhz, f adc =2 mhz 0 (4) 4. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. s t adc conversion time (sample+hold) 6 - sample capacitor loading time - hold conversion time 4 8 1/f adc
st7263bxx electrical characteristics doc id 7516 rev 8 163/186 figure 77. typical application with adc table 79. adc accuracy with v dd =5 v, f cpu = 8 mhz, f adc =4 mhz, r ain < 10 ? symbol parameter typ max (1)(2) 1. data based on characterization results over t he whole temperature range, not tested in production. 2. data based on characterization results, to guarantee 99 .73% within max value from 0 to 70 c ( 3s distribution limits). |e t | total unadjusted error (3) 3. adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6a and the effect on the adc accuracy is a loss of 1 lsb for each 10k increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst- case conditions for injection: - negative injection - injection to an input with analog capabilit y, adjacent to the enabled analog input - at 5v v dd supply, and worst case temperature. 1.5 2 |e o| offset error (3) 0.5 1 |e g| gain error (3) 0.5 1.5 |e d | differential linearity error (3) 11.5 |e l | integral linearity error (3) 11.5 ainx st72xxx c io ~2pf v dd i l 1 a v t 0.6v v t 0.6v v ain r ain v dda v ssa 0.1 f v dd adc
electrical characteristics st7263bxx 164/186 doc id 7516 rev 8 figure 78. adc accura cy characteristics 1. (1) example of an actual transfer curve; (2) the ideal transfer curve; (3) end point correlation line. 2. e t =total unadjusted error: maximum deviation bet ween the actual and the ideal transfer curves. e o =offset error: deviation between the firs t actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 256 ---------------------------------------- - = v in (lsb ideal ) digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa
st7263bxx package characteristics doc id 7516 rev 8 165/186 14 package characteristics in order to meet environmental requirements, st offers this device in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package characteristics st7263bxx 166/186 doc id 7516 rev 8 14.1 package mechanical data figure 79. 32-pin plastic dual in-line package, shrink 400-mil width, package outline d b1 b e a a1 a2 l e1 e ec c ea eb table 80. 32-pin plastic dual in-line package, shrink 400-mil width, package mechanical data dim. mm inches (1) min typ max min typ max a 3.560 3.760 5.080 0.1400 0.1480 0.2000 a1 0.510 0.0200 a2 3.050 3.560 4.570 0.1200 0.1400 0.1800 b 0.360 0.460 0.580 0.0140 0.0180 0.0230 b1 0.760 1.020 1.400 0.0300 0.0400 0.0550 c 0.200 0.250 0.360 0.0080 0.0100 0.0140 d 27.430 28.450 1.0800 1.1000 1.1200 e 9.910 10.410 11.050 0.3900 0.4100 0.4350 e1 7.620 8.890 9.400 0.3000 0.3500 0.3700 e 1.780 0.0700 ea 10.160 0.4000 eb 12.700 0.5000 ec 1.400 0.0550 l 2.540 3.050 3.810 0.1000 0.1200 0.15000 number of pins n32 1. values in inches are converted from mm and rounded to 4 decimal digits.
st7263bxx package characteristics doc id 7516 rev 8 167/186 figure 80. 34-pin plastic small outline package, 300-mil width, package outline h x 45 c l a a1 e b d h e table 81. 34-pin plastic small outline package, 300-mil width, package mechanical data dim. mm inches (1) min typ max min typ max a 2.464 2.642 0.0970 0.1040 a1 0.127 0.292 0.0050 0.0120 b 0.356 0.483 0.0140 0.0190 c 0.231 0.318 0.0090 0.0130 d 17.729 18.059 0.6980 0.7110 e 7.417 7.595 0.2920 0.2990 e 1.016 0.0400 h 10.160 10.414 0.4000 0.4100 h 0.635 0.737 0.0250 0.0290 0 8 0 8 l 0.610 1.016 0.0240 0.0400 number of pins n34 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics st7263bxx 168/186 doc id 7516 rev 8 figure 81. 24-pin plastic small outline package, 300-mil width package outline e 12 e d c h 13 24 1 b 9u_me a1 l a1 h x 45 a ddd table 82. 24-pin plastic small outline package, 300-mil width package mechanical data dim. mm inches (1) min typ max min typ max a 2.350 2.650 0.0930 0.1040 a1 0.100 0.300 0.0040 0.0120 b 0.330 0.510 0.0130 0.0200 c 0.230 0.320 0.0090 0.0130 d 15.200 15.600 0.5990 0.6140 e 7.400 7.600 0.2910 0.2990 e 1.270 0.0500 h 10.000 10.650 0.3940 0.4190 h 0.250 0.750 0.0100 0.0300 0 8 0 8 l 0.400 1.270 0.0160 0.0500 ddd 0.100 0.0040 number of pins n24 1. values in inches are converted from mm and rounded to 4 decimal digits.
st7263bxx package characteristics doc id 7516 rev 8 169/186 figure 82. 48-pin low profile quad flat package outline 5b_me l a1 l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 table 83. 48-pin low profile quad flat package mechanical data dim. mm inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0060 a2 1.350 1.400 1.450 0.0530 0.0551 0.0570 b 0.170 0.220 0.270 0.0070 0.0087 0.0110 c 0.090 0.200 0.0040 0.0080 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 0 3.5 7 0 3.5 7 ccc 0.080 0.0031 number of pins n48 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics st7263bxx 170/186 doc id 7516 rev 8 figure 83. 40-lead very thin fine pitch quad flat no-lead package outline seating plane a d2 1 2 pin #1 id type c radius d e a1 a3 a2 b e e2 l table 84. 40-lead very thin fine pitch quad flat no-lead package mechanical data dim. mm inches (1) min typ max min typ max a 0.800 0.900 1.000 0.0315 0.0354 0.0394 a1 0.020 0.050 0.0008 0.0020 a2 0.650 1.000 0.0260 0.0390 a3 0.200 0.0080 b 0.180 0.250 0.300 0.0070 0.0100 0.0120 d 5.850 6.000 6.150 0.2300 0.2360 0.2420 d2 2.750 2.90 3.050 0.1080 0.1140 0.1200 e 5.850 6.000 6.150 0.2300 0.2360 0.2420 e2 2.750 2.900 3.050 0.1080 0.1140 0.1200 e 0.500 0.0200 l 0.300 0.400 0.500 0.0120 0.0160 0.0200 number of pins n40 1. values in inches are converted from mm and rounded to 4 decimal digits.
st7263bxx package characteristics doc id 7516 rev 8 171/186 14.2 thermal characteristics 14.3 soldering and glueability information recommended glue for smd plastic packages dedicated to molding compound with silicone: heraeus: pd945, pd955 loctite: 3615, 3298 table 85. thermal characteristics symbol ratings value unit r thja package thermal resistance (junction to ambient) sdip32 so34 so24 lqfp48 qfn40 60 75 70 80 34 c/w p d power dissipation (1) 1. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user with the formula: p d =p int + p port where p int is the chip internal power (i dd x v dd ) and p port the port power dissipation depending on the ports used in the application. 500 mw t jmax maximum junction temperature (2) 2. the maximum chip-junction temperature is based on technology characteristics. 150 c
device configuration and ordering information st7263bxx 172/186 doc id 7516 rev 8 15 device configuration and ordering information each device is available for production in user programmable versions (high density flash). st72f63b flash devices are shipped to customers with a default content (ffh). this implies that flash devices have to be configured by the customer using the option byte while the rom devices are factory-configured. 15.1 option byte the option byte allows the hardware configuration of the microcontroller to be selected. the option byte has no address in the memory map and can be accessed only in programming mode using a standard st7 programming tool. the default contents of the flash is fixed to f7h. this means that all the options have ?1? as their default value, except lv d. in rom devices, the option byte is fixed in hardware by the rom code. option byte 7 0 -- -- wdg sw wd halt lvd -- osc 24/12 fmp_r opt 7:6 reserved opt 5 wdgsw hardware or software watchdog this option bit selects the watchdog type. 0: hardware enabled 1: software enabled opt 4 wdhalt watchdog and halt mode this option bit determines if a reset is ge nerated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation wh en entering halt mode opt 3 lv d low voltage dete ctor selection this option bit selects the lvd. 0: lvd enabled 1: lvd disabled note: important: on st7263bk1m1, st7263bk2m1, st7263bk2b1, and st7263bk2b1 rom devices, this option bit is forced by st to 0 (lvd always enabled).
st7263bxx device configuration and ordering information doc id 7516 rev 8 173/186 15.2 device ordering informatio n and transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended (see section 15.2 ). refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on contractual points. opt 2 reserved. opt 1 osc24/12 oscillator selection this option bit selects the clock divider used to drive the usb interface at 6mhz. 0: 24 mhz oscillator 1: 12 mhz oscillator opt 0 fmp_r flash memory readout protection this option indicates if the user flas h memory is protected against readout. readout protection, when selected, provi des a protection against program memory content extraction and against write access to flash memory. erasing the option bytes when the fmp_r option is selected, causes the whole user memory to be erased first and the device can be reprogrammed. refer to the st7 flash programming reference manual and section 4.3.1: readout protection for more details. 0: readout protection enabled 1: readout protection disabled table 86. supported order codes sales type (1)(2) program memory (bytes) ram (bytes) package st72f63bh6t1 32k flash 1024 lqfp48 st72f63bd6u1 qfn40 st72f63bk6m1 so34 st72f63bk6b1 sdip32 st72f63be6m1 so24 st72f63bh4t1 16k flash 512 lqfp48 st72f63bk4m1 so34 st72f63bk4b1 sdip32 st72f63be4m1 so24
device configuration and ordering information st7263bxx 174/186 doc id 7516 rev 8 15.3 development tools development tools for the st7 microcontrollers include a complete range of hardware systems and software tools from stmicroelectronics and third-party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 15.3.1 evaluation tool s and starter kits st offers complete, affordable starter kits and full-featured evaluation boards that allow you to evaluate microcontroller features and quickly start developing st7 applications. starter kits are complete, affordable hardware/software tool packages that include features and samples to to help you quickly start developing your application. st evaluation boards are open-design, embedded systems, which ar e developed and docum ented to serve as references for your application design. they include sample application software to help you demonstrate, learn about and implement your st7?s features. 15.3.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assembler-linker toolchain, which are all seamlessly integrated in the st7 integrated development environments in order to facilit ate the debugging and fine-tuning of your application. the cosmic c compiler is available in a free version that outputs up to 16k of code. the range of hardware tools includes full-featured st7-emu3 series emulators and the low-cost rlink in-circuit debugger/programmer. these tools are supported by the st7 toolset from stmicroelectronics, which includes the stvd7 integrated development st72f63bh2t1 8k flash 384 lqfp48 st72f63bk2u1 qfn40 st72f63bk2m1 so34 st72f63bk2b1 sdip32 st72f63be2m1 so24 st72f63bk1m1 4k flash 384 so34 st72f63bk1b1 sdip32 st72f63be1m1 so24 st7263bk2m1/xxx 8k rom 384 so34 st7263bk2b1/xxx sdip32 st7263bk1m1/xxx 4k rom 384 so34 st7263bk1b1/xxx sdip32 1. /xxx stands for the rom code na me assigned by st microelectronics. 2. contact st sales office for fastrom product availability. table 86. supported order codes (continued) sales type (1)(2) program memory (bytes) ram (bytes) package
st7263bxx device configuration and ordering information doc id 7516 rev 8 175/186 environment (ide) with high-level language debugger, editor, project manager and integrated programming interface. 15.3.3 programming tools during the development cycle, the st7-emu3 series emulators and the rlink provide in- circuit programming capability fo r programming the flash microc ontroller on your application board. in addition st provides dedicated programming tools including the st7-epb programming boards , which include all the sockets required to program any of the devices in a specific st7 sub-family. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment. 15.3.4 order codes for st7263bx development tools for additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu. table 87. development tool order codes for the st7263bx family mcu starter kit evaluation board emulator in-circuit debugger/programmer dedicated programmer st7263bx st72f63b- sk/rais st7mdtuls -eval st7mdtu3- emu3 stx-rlink st7mdtu3- epb
device configuration and ordering information st7263bxx 176/186 doc id 7516 rev 8 figure 84. option list st7263b microcontroller option list (last update: may 2009) customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rom code must be sent in .s19 format. hex extension cannot be processed. stmicroelectronics references: device type/memory size/package (check only one option): ------------|----------------|----------------|----------------|---------------- |rom device: | 4k | 8k | 16k | 32k | -------------|----------------|----------------|----------------|----------------| sdip32: |[ ] st7263bk1b1 |[ ] st7263bk2b1 | | | so34: |[ ] st7263bk1m1 |[ ] st7263bk2m1 | | | -------------|----------------|----------------|----------------|----------------| flash | 4k | 8k | 16k | 32k | -------------|----------------|----------------|----------------|----------------| so24: |[ ] st72f63be1m1|[ ] st72f63be2m1|[ ] st72f63be4m1|[ ] st72f63be6m1| sdip32: |[ ] st72f63bk1b1|[ ] st72f63bk2b1|[ ] st72f63bk4b1|[ ] st72f63bk6b1| so34: |[ ] st72f63bk1m1|[ ] st72f63bk2m1|[ ] st72f63bk4m1|[ ] st72f63bk6m1| qfn40 | |[ ] st72f63bk2u1| |[ ] st72f63bd6u1| lqfp48: | |[ ] st72f63bh2t1|[ ] st72f63bh4t1|[ ] st72f63bh6t1| -------------|----------------|----------------|----------------|----------------| die form: | 4k | 8k | 16k | 32k | -------------|----------------|----------------|----------------|-----------------| 24-pin: |[ ] (as e1m1) |[ ] (as e2m1) |[ ] (as e4m1) |[ ] (as e6m1) | 32-pin: |[ ] (as k1b1) |[ ] (as k2b1) |[ ] (as k4b1) |[ ] (as k6b1) | 34-pin: |[ ] (as k1m1) |[ ] (as k2m1) |[ ] (as k4m1) |[ ] (as k6m1) | 40-pin: | |[ ] (as h2u1) | |[ ] (as d6u1) | 48-pin: | |[ ] (as h2t1) |[ ] (as h4t1) |[ ] (as h6t1) | conditioning (check only one option) : --------------------------------------|----------------------------------------- packaged product | die product (dice tested at 25c only) | --------------------------------------|----------------------------------------- [ ] tape & reel (so package only) | [ ] tape & reel [ ] tube | [ ] inked wafer | [ ] sawn wafer on sticky foil special marking ( rom only): [ ] no [ ] yes "_ _ _ _ _ _ _ _ _ _ _ _ _" authorized characters are letters, digits, '.', '-', '/' and spaces only. for marking, one line is possible with a maximum of 13 characters. watchdog selection: [ ] software activation [ ] hardware activation halt when watchdog on: [ ] reset [ ] no reset lvd reset * [ ] disabled* [ ] enabled* * lvd is forced to 0 (lvd always enabled) for 4k and 8k rom devices (sales types st7263bk1b1, st7263bk2b1, st7263bk1m1, st72bk2m1 only) oscillator selection: [ ] 24 mhz. [ ] 12 mhz. readout protection: [ ] disabled [ ] enabled date . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . .
st7263bxx device configuration and ordering information doc id 7516 rev 8 177/186 15.4 st7 application notes table 88. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the readout protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative input voltages example drivers an 969 sci communication between st7 and pc an 971 i2c communication between st7 and m24cxx eeprom an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wakeup on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad
device configuration and ordering information st7263bxx 178/186 doc id 7516 rev 8 an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16-bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) impl ementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i 2 c peripherals an1753 software uart using 12-bit art an1947 st7mc pmac sine wave motor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits vs industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st 72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st 72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite 1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator table 88. st7 application notes (continued) identification description
st7263bxx device configuration and ordering information doc id 7516 rev 8 179/186 an1014 how to minimize the st7 power consumption an1015 software techniques for improv ing microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscillator an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop so ftware key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an1039 st7 math utility routines an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ programming) an1446 using the st72521 emulator to debug an st72324 target application an1477 emulated data eeprom with xflash memory an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) dr ivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) im plementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) table 88. st7 application notes (continued) identification description
device configuration and ordering information st7263bxx 180/186 doc id 7516 rev 8 an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via i 2 c an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigm a-delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 88. st7 application notes (continued) identification description
st7263bxx known limitations doc id 7516 rev 8 181/186 16 known limitations 16.1 pa2 limitation with ocmp1 enabled description this limitation affects only rev b flash devi ces (with internal sales type 72f63bxxxxx$x7 ) ; it has been corrected in rev w flash devices (with internal sales type 72f63bxxxxx$x9 ) . note: refer to figure 85 on page 183 when output compare 1 function (ocmp1) on pin pa6 is enabled by setting the oc1e bit in the tcr2 register, pin pa2 is also affected. in particular, pa2 is switched to its alternate function mode, scl. as a consequence, the pa2 pin is forced to be floating (steady level of i 2 c clock) even if port configuration (paddr+padr) has set it as output low. however, it can be still used as an input or can be controlled by the i 2 c cell when enabled (where i 2 c is available). 16.2 unexpected reset fetch description if an interrupt request occurs while a "pop cc" instruction is executed, the interrupt controller does not reco gnise the source of t he interrupt and, by default, passes the reset vector address to the cpu. workaround to solve this issue, a "pop cc" instruction mu st always be preceded by a "sim" instruction. 16.3 usb behavior with lvd disabled description if the lvd is disabled on 4k and 8k rom devices (st7263bk1m1, st72bk2m1, st7263bkb1, st7263bk2b1 only), the usb is disabled by hardware. the lvd is consequently forced by st to ?0? (lvd enabled). refer to the st7263bx option list for details. 16.4 i 2 c multimaster description in multimaster configurations, if the st7 i 2 c receives a start condition from another i 2 c master after the start bit is set in the i2ccr register and before the start condition is generated by the st7 i 2 c, it may ignore the start condition from the other i 2 c master. in this case, the st7 master will receive a nack from the other device. on reception of the nack, st7 can send a re-start and slave address to re-initiate communication
known limitations st7263bxx 182/186 doc id 7516 rev 8 16.5 halt mode power consumption with adc on description if the a/d converter is being used when halt mode is entered, the power consumption in halt mode may exceed the maximum specified in the datasheet. workaround switch off the adc by software (adon=0) before executing a halt instruction. 16.6 sci wrong break duration description a single break characte r is sent by setting and resetting the sbk bit in the scicr2 register. in some cases, the break character may have a longer duration than expected: - 20 bits instead of 10 bits if m=0 - 22 bits instead of 11 bits if m=1. in the same way, as long as the sbk bit is se t, break characters are sent to the tdo pin. this may generate one break more than expected. occurrence the occurrence of the problem is random and proportional to the baudrate. with a transmit frequency of 19200 baud (fcpu=8mhz and scibrr=0xc9), the wrong break duration occurrence is around 1%. workaround if this wrong duration is not compliant with th e communication protocol in the application, software can request that an idle line be generated before the break character. in this case, the break duration is always correct assuming the application is not doing anything between the idle and the break. this can be ensured by temporarily disabling interrupts. the exact sequence is: 1. disable interrupts 2. reset and set te (idle request) 3. set and reset sbk (break request) 4. re-enable interrupts
st7263bxx known limitations doc id 7516 rev 8 183/186 figure 85. identifying silicon revision from device marking and box label stmicroelectronics bulk id marking trace code total qty type xxxxxxxxxxxx xxxxxxxxxx b xxxxxxxxx xx xx xx xxxxxxxxxxx $x7 st7xxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 1. identify the silicon revision letter from ei ther the device package or the box label. for example, ? b ?, etc. 2. if the revision letter is not present, obtain the silicon revision by contacting your local st office with the trace code information printed on either the box label or the device device package (so34 shown) example box label the silicon revision can be iden tified either by rev letter or obtained via a trace code. silicon rev trace code silicon rev
revision history st7263bxx 184/186 doc id 7516 rev 8 17 revision history table 89. document revision history date revision changes 27-may-05 3 new revision created by merging 32k flash and non-32k flash datasheets together. memory map, figure 7 , expanded to handle all devices and memory sizes. operating conditions with lvd values modified, section 13.3.1: operating co nditions with low voltage detector (lvd) . supply current characteristics values and notes updated, section 13.4: supply current characteristics . idd run and wait graphs replaced, figure 55 and figure 56 on page 143 . control timing characteristics modified, section table 62.: control timing characteristics . flash memory table notes and t prog typical value updated, section 13.6.1: flash memory . notes added for i/o port pin characteristics table, section table 70.: general characteristics . note for r pu modified, removing reference to data characterization, section table 70. i pu and r pu graphs added, figure 61 and figure 62 on page 150 . notes updated for usb low speed electrical characteristics. output voltage/current graphs added, figures figure 63. - figure 72. thermal characteristics added for so24 and tqfp48 packages, section 14.2: thermal characteristics . important note added for opt 3 option byte (lvd), section 15.1: option byte . supported part numbers table updated with full sales type codes, ta bl e 8 6 . option list updated with all device options. important notes updated with ?usb b ehavior with lvd disabled?, section 16.3: usb behavior with lvd disabled . clock block diagram redrawn, figure 18 on page 36 . dfu added to title and features list. removed unnecessary notes related to typical values (already mentioned in section 13.1.2: typical values ) in electrical characteristic tables sections: section 13.3.1 , section 13.4 , section 13.6.1 , section table 70. , section table 72. and section 13.11 . added note for max values in adc accuracy, section 13.11 . static latch up (lu) class tested only for t a =25c, section : static latchup (lu) 19-sep-05 4 flash memory minimum data retention increased to 40 years, section 13.6.1: flash memory af bit text modified concerning scl, i 2 c chapter section 11.5.7: register description reference made to the flash programming reference manual for flash timing values reset pulse generated by wdg changed to 30 s, section 11.1: watchdog timer (wdg) modified text in section 11.3: serial communications interface (sci) , adding parity error as an interrupt added ecopack information in section 14: package characteristics modified i s value and corresponding note in section table 70.: general characteristics 06-apr-06 5 32k and 8k qfn40 packages added 4k so24 package added tqfp package renamed to lqfp
st7263bxx revision history doc id 7516 rev 8 185/186 03-oct-06 6 important notes section renamed to known limitations, section 16: known limitations new pa2 limitation added, section 16: known limitations figure 85 on page 183 added for silicon revision identification 20-aug-07 7 new 16k lqfp48 package added to product family. note added to v oh data in section table 71.: output driving current list of supported partnumber availability updated, ta b l e 8 6 download address updated in section 15.3.4: order codes for st7263bx development tools and option list. 12-jun-2009 8 removed fastrom devices as well as 32 and 16 kbyte rom devices. added caution note in section 6.1: reset . replaced ccr by cc (condition code) register when the i bit is concerned. updated alternate function condition for pb4 to pb7 in ta b l e 1 3 : po r t b description . renamed t dog and t dogl , t wdg and t wdgl . removed emc protective circuitry in figure 74: reset pin protection when lvd is disabled (device works correctly without these components). removed all mentions to spi interface. removed dynamic latchup in section 13.7.3: absolute maximum ratings (electrical sensitivity) . modified notes below table 85: thermal characteristics . update table 86: supported order codes and figure 84: option list . updated ecopack text, and removed recommended wave soldering profile and recommended reflow soldering oven profile, in section 14: package characteristics . table 89. document revision history (continued) date revision changes
st7263bxx 186/186 doc id 7516 rev 8 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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